NBC12430, NBC12430A
3.3V/5V Programmable PLL
Synthesized Clock
Generator
50 MHz to 800 MHz
The NBC12430 and NBC12430A are general purpose, PLL based
synthesized clock sources. The VCO will operate over a frequency
range of 400 MHz to 800 MHz. The VCO frequency is sent to the
N−output divider, where it can be configured to provide division ratios
of 1, 2, 4, or 8. The VCO and output frequency can be programmed
using the parallel or serial interfaces to the configuration logic. Output
frequency steps of 250 kHz, 500 kHz, 1.0 MHz, 2.0 MHz can be
achieved using a 16 MHz crystal, depending on the output dividers
settings. The PLL loop filter is fully integrated and does not require
any external components.
Features
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MARKING
DIAGRAMS
1 28
NBC12430xG
PLCC−28
FN SUFFIX
CASE 776
AWLYYWW
•
•
•
•
•
•
•
•
•
•
•
•
−40°C
to 85°C Ambient Operating Temperature (NBC12430A)
•
Pb−Free Packages are Available
Best−in−Class Output Jitter Performance,
±20
ps Peak−to−Peak
50 MHz to 800 MHz Programmable Differential PECL Outputs
Fully Integrated Phase−Lock−Loop with Internal Loop Filter
Parallel Interface for Programming Counter and Output Dividers
During Powerup
Minimal Frequency Overshoot
Serial 3−Wire Programming Interface
Crystal Oscillator Interface
Operating Range: V
CC
= 3.135 V to 5.25 V
CMOS and TTL Compatible Control Inputs
Pin and Function Compatible with Motorola MC12430 and
MPC9230
0°C to 70°C Ambient Operating Temperature (NBC12430)
LQFP−32
FA SUFFIX
CASE 873A
NBC12
430x
AWLYYWWG
1
1
32
QFN32
MN SUFFIX
CASE 488AM
NBC12
430x
AWLYYWWG
G
x
A
WL, L
YY, Y
WW, W
G or
G
= Blank or A
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 16 of this data sheet.
©
Semiconductor Components Industries, LLC, 2010
October, 2010
−
Rev. 13
1
Publication Order Number:
NBC12430/D
NBC12430, NBC12430A
The following gives a brief description of the functionality of the NBC12430 and NBC12430A Inputs and Outputs. Unless
explicitly stated, all inputs are CMOS/TTL compatible with either pullup or pulldown resistors. The PECL outputs are capable
of driving two series terminated 50
W
transmission lines on the incident edge.
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Pin Name
Function
Description
INPUTS
XTAL1, XTAL2
S_LOAD*
Crystal Inputs
CMOS/TTL Serial Latch Input
(Internal Pulldown Resistor)
CMOS/TTL Serial Data Input
(Internal Pulldown Resistor)
CMOS/TTL Serial Clock Input
(Internal Pulldown Resistor)
CMOS/TTL Parallel Latch Input
(Internal Pullup Resistor)
These pins form an oscillator when connected to an external series−resonant
crystal.
This pin loads the configuration latches with the contents of the shift registers. The
latches will be transparent when this signal is HIGH; thus, the data must be stable
on the HIGH−to−LOW transition of S_LOAD for proper operation.
This pin acts as the data input to the serial configuration shift registers.
This pin serves to clock the serial configuration shift registers. Data from S_DATA
is sampled on the rising edge.
This pin loads the configuration latches with the contents of the parallel inputs
.The latches will be transparent when this signal is LOW; therefore, the parallel
data must be stable on the LOW−to−HIGH transition of P_LOAD for proper opera-
tion.
These pins are used to configure the PLL loop divider. They are sampled on the
LOW−to−HIGH transition of P_LOAD. M[8] is the MSB, M[0] is the LSB.
These pins are used to configure the output divider modulus. They are sampled
on the LOW−to−HIGH transition of P_LOAD.
Active HIGH Output Enable. The Enable is synchronous to eliminate possibility of
runt pulse generation on the F
OUT
output.
This pin can be used as the PLL Reference
This pin selects between the crystal and the FREF_EXT source for the PLL refer-
ence signal. A HIGH selects the crystal input.
S_DATA*
S_CLOCK*
P_LOAD**
M[8:0]**
N[1:0]**
OE**
FREF_EXT*
XTAL_SEL**
OUTPUTS
F
OUT
, F
OUT
TEST
POWER
V
CC
PLL_V
CC
GND
−
Positive Supply for the Logic
Positive Supply for the PLL
Negative Power Supply
Exposed Pad for QFN−32 only
The positive supply for the internal logic and output buffer of the chip, and is con-
nected to +3.3 V or +5.0 V.
This is the positive supply for the PLL and is connected to +3.3 V or +5.0 V.
These pins are the negative supply for the chip and are normally all connected to
ground.
The Exposed Pad (EP) on the QFN−32 package bottom is thermally connected to
the die for improved heat transfer out of package. The exposed pad must be at-
tached to a heat−sinking conduit. The pad is electrically connected to GND.
PECL Differential Outputs
PECL Output
These differential, positive−referenced ECL signals (PECL) are the outputs of the
synthesizer.
The function of this output is determined by the serial configuration bits T[2:0].
CMOS/TTL PLL Loop Divider
Inputs (Internal Pullup Resistor)
CMOS/TTL Output Divider Inputs
(Internal Pullup Resistor)
CMOS/TTL Output Enable Input
(Internal Pullup Resistor)
CMOS/TTL Input
(Internal Pulldown Resistor)
CMOS/TTL Input
(Internal Pullup Resistor)
* When left Open, these inputs will default LOW.
** When left Open, these inputs will default HIGH.
Table 3. PIN FUNCTION DESCRIPTION
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4
NBC12430, NBC12430A
Table 4. ATTRIBUTES
Characteristics
Internal Input Pulldown Resistor
Internal Input Pullup Resistor
ESD Protection
Human Body Model
Machine Model
Charged Device Model
Pb Pkg
PLCC
LQFP
QFN
Flammability Rating
Transistor Count
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
Oxygen Index: 28 to 34
Level 1
Level 2
Level 1
Value
75 kW
37.5 kW
> 2 kV
> 150 V
> 1 kV
Pb−Free Pkg
Level 3
Level 2
Level 1
Moisture Sensitivity (Note 1)
UL 94 V−0 @ 0.125 in
2011
Table 5. MAXIMUM RATINGS
Symbol
V
CC
V
I
I
out
T
A
Positive Supply
Input Voltage
Output Current
Operating Temperature Range
Parameter
Condition 1
GND = 0 V
GND = 0 V
Continuous
Surge
NBC12430
NBC12430A
V
I
V
CC
Condition 2
Rating
6
6
50
100
0 to 70
−40
to +85
−65
to +150
0 lfpm
500 lfpm
Standard Board
0 lfpm
500 lfpm
Standard Board
0 lfpm
500 lfpm
2S2P
Pb
Pb−Free
<3 sec @ 248°C
<3 sec @ 260°C
PLCC−28
PLCC−28
PLCC−28
LQFP−32
LQFP−32
LQFP−32
QFN−32
QFN−32
QFN−32
63.5
43.5
22 to 26
80
55
12 to 17
31
27
12
265
265
Units
V
V
mA
mA
°C
T
stg
q
JA
q
JC
q
JA
q
JC
q
JA
q
JC
T
sol
Storage Temperature Range
Thermal Resistance (Junction−to−Ambient)
Thermal Resistance (Junction−to−Case)
Thermal Resistance (Junction−to−Ambient)
Thermal Resistance (Junction−to−Case)
Thermal Resistance (Junction−to−Ambient)
Thermal Resistance (Junction−to−Case)
Wave Solder
°C
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
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5
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