Ordering number : ENA2019
LV8747TA
Bi-CMOS LSI
PWM Constant-Current Control Stepping Motor
Driver and Switching Regulator Controller
Overview
http://onsemi.com
The LV8747TA is a PWM constant-current control stepping motor driver and switching regulator controller IC.
Features
•
Two circuits of PWM constant-current control stepping motor driver incorporated
•
Control of the stepping motor to W1-2 phase excitation possible
•
Output-stage push-pull composition enabling high-speed operation
•
Two circuits of switching regulator controller incorporated
•
Thermal shutdown circuit incorporated
•
Timer latch type short-circuit protection circuit incorporated
•
Motor driver control power incorporated
•
Output short-circuit protection circuit incorporated
•
Chopping frequency selectable
•
High-precision reference voltage circuit incorporated
•
Upper and lower regenerative diodes incorporated
Specifications
Absolute Maximum Ratings
at Ta = 25°C
Parameter
Supply voltage
Driver output peak current 1
Driver output continuous current 1
Driver output peak current 2
Driver output continuous current 2
Regulator output current
Allowable power dissipation 1
Allowable power dissipation 2
Operating temperature
Storage temperature
Symbol
VM max
MDIO peak1
MDIO max1
MDIO peak2
MDIO max2
SWIO max
Pd max1
Pd max2
Topr
Tstg
OUT1/OUT2 tw
≤
10ms, duty 20%
OUT1/OUT2
OUT3/OUT4 tw
≤
10ms, duty 20%
OUT3/OUT4
OUT5/OUT6 tw
≤
1μs
Independent IC
Our recommended four-layer substrate *1, *2
Conditions
Ratings
38
1.75
1.5
0.8
0.5
500
0.4
4.85
-20 to +85
-55 to +150
Unit
V
A
A
A
A
mA
W
W
°C
°C
*1 Specified circuit board : 100×100×1.6mm
3
: 4-layer glass epoxy printed circuit board
*2 For mounting to the backside by soldering, see the precautions.
Caution 1) Absolute maximum ratings represent the value which cannot be exceeded for any length of time.
Caution 2) Even when the device is used within the range of absolute maximum ratings, as a result of continuous usage under high temperature, high current,
high voltage, or drastic temperature change, the reliability of the IC may be degraded. Please contact us for the further details.
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating
Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
Semiconductor Components Industries, LLC, 2013
June, 2013
41112 SY 20120131-S00006 No.A2019-1/20
LV8747TA
Allowable Operating Ratings
at Ta = 25°C
Parameter
Supply voltage
Logic input voltage
VREF input voltage
Regulator output voltage
Regulator output current
Error amplifier input voltage
Timing capacity
Timing resistance
Triangular wave oscillation
frequency
Symbol
VM
VIN
VREF
VO
IO
VOA
CT
RT
FOSC
Conditions
Ratings
10 to 35
0 to 5
0 to 3
VM-5 to VM
0 to 200
0 to 3
100 to 15000
5 to 50
10 to 800
Unit
V
V
V
V
mA
V
pF
kΩ
kHz
Electrical Characteristics
at Ta = 25°C, VM = 24V, VREF = 1.5V
Parameter
General
VM current drain
Thermal shutdown temperature
Thermal hysteresis width
REG5 output voltage
Motor Drivers
[Charge pump block]
Boost voltage
Rise time
Oscillation frequency
Output block (OUT1/OUT2)
Output on resistance
RonU1
RonD2
Output leak current
Diode forward voltage
Output block (OUT3/OUT4)
Output on resistance
RonU2
RonD2
Output leak current
Diode forward voltage
Logic input block
Logic pin input current
IINL
IINH
Logic high-level input voltage
Logic low-level input voltage
Current control block
VREF input current
Chopping frequency
Threshold voltage of current setting
comparator
IREF
Fchop
VHH
VLH
VHL
Output short-circuit protection circuit
Charge current
Threshold voltage
IOCP
VthOCP
VOCP = 0V
15
0.8
20
1.0
25
1.2
μA
V
VREF = 1.5V
CHOP = 20kΩ
VREF = 1.5V, I0 = H, I1 = H
VREF = 1.5V, I0 = L, I1 = H
VREF = 1.5V, I0 = H, I1 = L
-0.5
45
0.291
0.191
0.093
62.5
0.300
0.200
0.100
75
0.309
0.209
0.107
μA
kHz
V
V
V
VINH
VINL
VIN = 0.8V
VIN = 5V
3
30
2.0
0.8
8
50
15
70
μA
μA
V
V
IOleak2
VD2
IO = -500mA, source side
IO = 500mA, sink side
VO = 35V
ID = -500mA
1.0
1.5
1.1
1.8
1.4
50
1.3
Ω
Ω
μA
V
IOleak1
VD1
IO = -1.5A, source side
IO = 1.5A, sink side
VO = 35V
ID = -1.5A
1.0
0.5
0.5
0.8
0.8
50
1.3
Ω
Ω
μA
V
VGH
tONG
Fcp
VM = 24V
VG = 10μF
CHOP = 20kΩ
90
28.0
28.7
50
120
29.8
100
150
V
ms
kHz
IM
TSD
ΔTSD
Vreg5
PS = “H”, no load
Design guarantee
Design guarantee
Ireg5 = -1mA
4.5
6
180
40
5.0
5.5
8
mA
°C
°C
V
Symbol
Conditions
min
Ratings
typ
max
Unit
Switching regulator Controller
[Reference voltage block]
REG25 output voltage
Input stability
Load stability
Internal regulator block
REGVM5 output voltage
VregVM5
VregVM5 = 1mA
VM-6.0
VM-5.0
V
Vreg25
VDLI
VDLO
Ireg25 = -1mA
VM = 10 to 35V
Ireg25 = 0 to -3mA
2.475
2.500
2.525
10
10
V
mV
mV
Continued on next page.
No.A2019-2/20
LV8747TA
Continued from preceding page.
Parameter
Triangular wave oscillator block
Oscillation frequency
Frequency fluctuation
Current setting pin voltage
Protective circuit block
Threshold voltage of comparator
Standby voltage
Source current
Threshold voltage
Latch voltage
Soft start circuit block
Source current
Latch voltage
ISOFT
VltSOFT
VSOFT = 0V
ISOFT = 40μA
1.3
1.6
1.9
100
μA
mV
VthFB
VstSCP
ISCP
VthSCP
VltSCP
ISCP = 40μA
FB5, FB6
ISCP = 40μA
VSCP = 0V
1.6
1.65
2.5
1.8
1.40
1.55
1.70
100
3.4
1.95
100
V
mV
μA
V
mV
FOSC
FDV
VRT
RT = 20kΩ, CT = 620pF
VM = 10 to 35V
RT = 20kΩ
0.91
72
80
1
0.98
88
5
1.05
kHz
%
V
Symbol
Conditions
min
Ratings
typ
max
Unit
Low-input malfunction preventive circuit block
Threshold voltage
Hysteresis voltage
Error amplifier block
Input offset voltage
Input offset current
Input bias current
OPEN open gain
Common-phase input voltage range
Common phase removal ratio
Max output voltage
Min output voltage
Output sink current
Output source current
PWM comparator block
Input threshold voltage
(Fosc = 10kHz)
Input bias current
MAX duty cycle 1
(Fosc = 80kHz)
MAX duty cycle 2
(Fosc = 160kHz)
MAX duty cycle 3
(Fosc = 10kHz)
Output block
Output ON resistance
RonU3
RonD3
Leak current
ILEAK
IO = -200mA, source side
IO = 200mA, sink side
VO = 35V
10
6
12
8
5
Ω
Ω
μA
Don3
Don2
VT100
VT0
IBDT
Don1
Duty cycle = 100%
Duty cycle = 0%
DT6 = 0.4V
5ch
Internally fixed
5ch
Internally fixed
6ch
VREG25 divided by 17kΩ and 8kΩ
94
92
56
65
74
0.95
0.49
1.01
0.52
1.07
0.55
1
V
V
μA
%
%
%
ViO
I iO
Iib
AV
VCM
CMRR
VOH
VOL
Isi
Iso
FB = 2.5V
FB = 2.5V
300
45
4.5
VM = 10 to 35V
80
5.0
0.2
600
75
0.5
1000
105
85
3.0
6
30
100
mV
nA
nA
dB
V
dB
V
V
μA
μA
VUT
VHIS
8.3
240
8.7
340
9.1
440
V
mV
No.A2019-3/20
LV8747TA
Pin Assignment
64
I14
63
I04
62
PS
61
VREF34
60
OCP
59
OCPM
58
OUT5
57
OUT6
56
REGVM5
55
GND
54
NON5
53
INV5
52
FB5
51
NON6
50
INV6
49
FB6
1
GND
2
PHA4
3
OUT4B
4
RNF4
5
OUT4A
6
VM34
DT6
48
RT
47
CT
46
REG25
45
REG5
44
SCP
43
LV8747TA
7
OUT3B
8
RNF3
9
OUT3A
10
PGND3
11
I03
12
I13
13
PHA3
14
I02
15
I12
PGND2
SOFT
42
VMSW
41
VREF12
40
CHOP
39
CP1
38
Top View
CP2
37
VG
36
I01
35
I11
34
PGND1
OUT2B
OUT2B
OUT2A
OUT2A
OUT1B
OUT1B
OUT1A
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
OUT1A
16
PHA2
PHA1
33
VM12
VM12
RNF2
RNF2
RNF1
RNF1
32
Package Dimensions
unit : mm (typ)
3422
TOP VIEW
9.0
7.0
0.5
SIDE VIEW
BOTTOM VIEW
Exposed Die-Pad
(4.0)
9.0
(4.0)
7.0
64
1 2
0.4
(0.5)
(1.0)
0.18
0.125
SIDE VIEW
1.2 MAX
0.1
SANYO : TQFP64L(7X7)
No.A2019-4/20
LV8747TA
6.0
Pd max – Ta
*1 With Exposed Die-Pad substrate
*2 Without Exposed Die-Pad
Allowable power dissipation, Pd max – W
4.85
Four-layer substrate *1
4.0
Four-layer substrate *2
2.40
2.0
2.52
1.25
0
–
20
0
20
40
60
80
100
Ambient temperature, Ta – °C
Substrate Specifications
(Substrate recommended for operation of LV8747TA)
Size
: 100mm × 100mm × 1.6mm (four-layer substrate [2S2P])
Material
: Glass epoxy
Copper wiring density : L1 = 85% / L4 = 90%
L1 : Copper wiring pattern diagram
L4 : Copper wiring pattern diagram
Cautions
1) The data for the case with the Exposed Die-Pad substrate mounted shows the values when 80% or more of the
Exposed Die-Pad is wet.
2) For the set design, employ the derating design with sufficient margin.
Stresses to be derated include the voltage, current, junction temperature, power loss, and mechanical stresses such as
vibration, impact, and tension.
Accordingly, the design must ensure these stresses to be as low or small as possible.
The guideline for ordinary derating is shown below :
(1)Maximum value 80% or less for the voltage rating
(2)Maximum value 80% or less for the current rating
(3)Maximum value 80% or less for the temperature rating
3) After the set design, be sure to verify the design with the actual product.
Confirm the solder joint state and verify also the reliability of solder joint for the Exposed Die-Pad, etc.
Any void or deterioration, if observed in the solder joint of these parts, causes deteriorated thermal conduction,
possibly resulting in thermal destruction of IC.
No.A2019-5/20
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