XC6126
Series
Ultra Small, Highly Accurate, Single Voltage Detector
ETR0214-005a
■GENERAL
DESCRIPTION
The XC6126 series is an ultra small, highly accurate CMOS single voltage detector with very low power consumption. The
device includes a highly accurate reference voltage source and uses laser trimming technologies, it maintains high accuracy
over the full operation temperature range.
The device is available in both CMOS and N-channel open drain output configurations.
Ultra small package USPN-4B02 is ideally suited for small design of portable devices and high densely mounting
applications. The conventional package SSOT-24 is also available for upper compatible replacements.
■APPLICATIONS
●
Microprocessor logic reset circuitry
■FEATURES
High Accuracy
Temperature Characteristics
Low Power Consumption
Operating Voltage Range
Detect Voltage Range
Output Configuration
Detect Logic
Packages
Environmentally Friendly
:
:
:
:
:
:
:
:
:
±0.8％
(25℃)
±50ppm
/℃ (TYP.)
0.6μA (TYP.) (Detect: V
DF
=1.8V, V
IN
=1.62V)
0.7μA (TYP.) (Release: V
DF
=1.8V, V
IN
=1.98V)
●
System battery life and charge voltage monitors
●
Memory battery back-up circuits
●
Power-on reset circuits
●
Power failure detection
0.7V½6.0V
1.5V½5.5V (0.1V increments)
N-channel open drain output
CMOS output
Active Low Reset
USPN-4B02, SSOT-24
EU RoHS Compliant, Pb Free
■TYPICAL
APPLICATION CIRCUIT
■
TYPICAL PERFORMANCE
CHARACTERISTICS
●Detect
Voltage vs. Ambient Temperature
XC6126x27A½
2.76
Detect Voltage: V
DFL
(V)
2.74
2.72
2.70
2.68
2.66
2.64
-50
-25
0
25
50
75
100
Ambient Temperature: Ta (℃)
1/16
XC6126
Series
■BLOCK
DIAGRAMS
* Diodes inside the circuits are ESD protection diodes and parasitic diodes.
* Diodes inside the circuits are ESD protection diodes.
■ABSOLUTE
MAXIMUM RATINGS
Ta=25℃
PARAMETER
Input Voltage
Output Current
XC6126C
(*1)
Output Voltage
XC6126N
(*2)
USPN-4B02
Power Dissipation
SSOT-24
Operating Temperature Range
Storage Temperature Range
Note:
(*1) CMOS Output
(*2) N-ch Open Drain Output
SYMBOL
V
IN
I
OUT
V
OUT
Pd
Topr
Tstg
RATING
V
SS
-0.3½+6.5
20
V
SS
-0.3½V
IN
+0.3≦6.5
V
SS
-0.3½+6.5
100
150
-40½+85
-55½+125
UNITS
V
mA
V
mW
o
o
C
C
3/16
XC6126
Series
■ELECTRICAL
CHARACTERISTICS
XC6126 Series
Ta=25℃
SYMBOL
V
IN
V
DFL
V
HYS
V
IN
=V
DFL
×0.9
V
DF(T)
=1.5½1.8V
V
DF(T)
=1.9½3.0V
V
DF(T)
=3.1½5.5V
V
IN
=V
DFL
×1.1
(*5)
V
DF(T)
=1.5½1.8V
V
DF(T)
=1.9½3.0V
V
DF(T)
=3.1½5.5V
V
IN
=0.7V,V
OUT
=0.5V(N-ch)
V
IN
=1.0V, V
OUT
=0.5V(N-ch)
V
IN
=2.0V
(*6)
, V
OUT
=0.5V(N-ch)
I
OUT1
CONDITIONS
V
DF(T)(*1)
=1.5½5.5V
(*2)
V
DF(T)
=1.5½5.5V
MIN.
0.7
(*3)
V
DF(T)
×0.992
V
DFL
×0.02
-
-
-
-
-
-
0.008
0.6
4.5
7.0
8.5
9.5
-
-
-
-
-
-
V
DF(T)
E-1
V
DFL
×0.05
0.6
0.7
0.9
0.7
0.8
1.0
0.2
1.5
7.0
10.0
11.5
13.0
-4.6
-0.01
0.01
±50
30
20
(*4)
PARAMETER
Operating Voltage
Detect Voltage
Hysteresis Width
TYP.
MAX.
6.0
V
DF(T)
×1.008
V
DFL
×0.08
1.3
1.5
1.85
1.55
1.75
2.25
-
-
-
UNITS
V
V
V
CIRCUIT
-
①
①
Supply Current 1
I
SS1
μA
②
Supply Current 2
I
SS2
μA
②
mA
V
IN
=3.0V
(*7)
③
Output Current
,V
OUT
=0.5V(N-ch)
-
-
-
-2.8
-
0.15
-
100
50
mA
μA
③
μA
ppm/℃
μs
μs
①
④
④
③
V
IN
=4.0V
(*8)
,V
OUT
=0.5V(N-ch)
V
IN
=5.0V
(*9)
,V
OUT
=0.5V(N-ch)
I
OUT2 (*10)
Leakage
Current
CMOS
Output
N-ch Open
Drain Output
V
IN
=6.0V,V
OUT
=5.5V(P-ch)
V
IN
=V
DFL
×0.9,V
OUT
=0V
I
LEAK
V
IN
=6.0V,V
OUT
=6.0V
∆V
DFL
/
(∆Topr・V
DFL
)
t
DF
t
DR
-40℃≦Topr≦85℃
V
IN
=V
DFL
×1.1
(*5)
→V
DFL
×0.9
V
IN
=V
DFL
×0.9→V
DFL
×1.1
(*5)
Temperature Characteristics
Detect Delay Time
(*11)
Release Delay Time
(*12)
Note:
(*1) V
DF(T)
: Nominal detect voltage
(*2) For the N-ch Open Drain, Rpull=1MΩ, Vpull-Up=V
IN
.
Rpull：An External Pull-up resistor
Vpull-Up：Pull-up Voltage
(*3)V
IN
voltage for V
OUT
≦0.3V
is under detect state.
(*4)For the detail value, please refer to “Voltage Table” in next page.
(*5) V
IN
=6.0V where V
DF(T)
= 5.5V.
(*6) For V
DF(T)
＞2.0V
products.
(*7) For V
DF(T)
＞3.0V
products.
(*8) For V
DF(T)
＞4.0V
products.
(*9) For V
DF(T)
＞5.0V
products.
(*10)For the XC6126C (CMOS output)
(*11) A time between V
IN
=V
DFL
and V
OUT
=V
DFL
×0.45
when V
IN
falls.
(*12) A time between V
IN
=V
DFL
+V
HYS
and V
OUT
=V
DFL
×0.55
when V
IN
rises.
4/16
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
