74LVC2G74-Q100
Single D-type flip-flop with set and reset; positive edge trigger
Rev. 1 — 24 December 2012
Product data sheet
1. General description
The 74LVC2G74-Q100 is a single positive-edge triggered D-type flip-flop. It has individual
data (D) inputs, clock (CP) inputs, set (SD) and reset (RD) inputs, and complementary
Q and Q outputs.
This device is fully specified for partial power-down applications using I
OFF
. The I
OFF
circuitry disables the output, preventing damaging backflow current through the device
when it is powered down.
The set and reset are asynchronous active LOW inputs and operate independently of the
clock input. Information on the data input is transferred to the Q output on the
LOW-to-HIGH transition of the clock pulse. The D inputs must be stable, one set-up time
prior to the LOW-to-HIGH clock transition for predictable operation. Schmitt trigger action
at all inputs makes the circuit highly tolerant to slower input rise and fall times.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from
40 C
to +85
C
and from
40 C
to +125
C
Wide supply voltage range from 1.65 V to 5.5 V
5 V tolerant inputs for interfacing with 5 V logic
High noise immunity
Complies with JEDEC standard:
JESD8-7 (1.65 V to 1.95 V)
JESD8-5 (2.3 V to 2.7 V)
JESD8-B/JESD36 (2.7 V to 3.6 V)
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0
)
24
mA output drive (V
CC
= 3.0 V)
CMOS low power consumption
Latch-up performance exceeds 250 mA
Direct interface with TTL levels
Inputs accept voltages up to 5 V
Multiple package options
NXP Semiconductors
74LVC2G74-Q100
Single D-type flip-flop with set and reset; positive edge trigger
3. Ordering information
Table 1.
Ordering information
Package
Temperature
range
74LVC2G74DP-Q100
40 C
to +125
C
74LVC2G74DC-Q100
40 C
to +125
C
Name
Description
Version
SOT505-2
Type number
TSSOP8 plastic thin shrink small outline package; 8 leads;
body width 3 mm; lead length 0.5 mm
VSSOP8 plastic very thin shrink small outline package; 8 leads; SOT765-1
body width 2.3 mm
4. Marking
Table 2.
Marking codes
Marking code
[1]
V74
V74
Type number
74LVC2G74DP-Q100
74LVC2G74DC-Q100
[1]
The pin 1 indicator is located on the lower left corner of the device, below the marking code.
5. Functional diagram
SD
D
CP
SD
D
CP
FF
Q
RD
RD
001aah725
Q
Q
S
Q
C1
1D
R
001aah726
Fig 1.
Logic symbol
Fig 2.
IEC logic symbol
74LVC2G74_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 24 December 2012
2 of 17
NXP Semiconductors
74LVC2G74-Q100
Single D-type flip-flop with set and reset; positive edge trigger
Q
C
C
C
C
D
C
RD
C
C
Q
C
SD
mna421
CP
C
C
Fig 3.
Logic diagram
6. Pinning information
6.1 Pinning
/9&*4
&3
'
4
*1'
DDD
9
&&
6'
5'
4
Fig 4.
Pin configuration SOT505-2 and SOT765-1
6.2 Pin description
Table 3.
Symbol
CP
D
Q
GND
Q
RD
SD
V
CC
Pin description
Pin
1
2
3
4
5
6
7
8
Description
clock input (LOW-to-HIGH, edge-triggered)
data input
complement output
ground (0 V)
true output
asynchronous reset-direct input (active LOW)
asynchronous set-direct input (active LOW)
supply voltage
74LVC2G74_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 24 December 2012
3 of 17
NXP Semiconductors
74LVC2G74-Q100
Single D-type flip-flop with set and reset; positive edge trigger
7. Functional description
Table 4.
Input
SD
L
H
L
[1]
Function table for asynchronous operation
[1]
Output
RD
H
L
L
CP
X
X
X
D
X
X
X
Q
H
L
H
Q
L
H
H
H = HIGH voltage level; L = LOW voltage level; X = don’t care.
Table 5.
Input
SD
H
H
[1]
Function table for synchronous operation
[1]
Output
RD
H
H
CP
D
L
H
Q
n+1
L
H
Q
n+1
H
L
H = HIGH voltage level; L = LOW voltage level;
= LOW-to-HIGH CP transition; Q
n+1
= state after the next LOW-to-HIGH CP transition.
8. Limiting values
Table 6.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
I
IK
V
I
I
OK
V
O
I
O
I
CC
I
GND
P
tot
T
stg
[1]
[2]
[3]
Parameter
supply voltage
input clamping current
input voltage
output clamping current
output voltage
output current
supply current
ground current
total power dissipation
storage temperature
Conditions
V
I
< 0 V
[1]
Min
0.5
50
0.5
-
[1][2]
[1][2]
Max
+6.5
-
+6.5
50
+6.5
50
100
-
300
+150
Unit
V
mA
V
mA
V
mA
mA
mA
mW
C
V
O
> V
CC
or V
O
< 0 V
Active mode
Power-down mode
V
O
= 0 V to V
CC
0.5
0.5
-
-
100
V
CC
+ 0.5 V
T
amb
=
40 C
to +125
C
[3]
-
65
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
When V
CC
= 0 V (Power-down mode), the output voltage can be 5.5 V in normal operation.
For TSSOP8 packages: above 55
C
the value of P
tot
derates linearly with 2.5 mW/K.
For VSSOP8 packages: above 110
C
the value of P
tot
derates linearly with 8.0 mW/K.
74LVC2G74_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 24 December 2012
4 of 17
NXP Semiconductors
74LVC2G74-Q100
Single D-type flip-flop with set and reset; positive edge trigger
9. Recommended operating conditions
Table 7.
Symbol
V
CC
V
I
V
O
T
amb
t/V
Operating conditions
Parameter
supply voltage
input voltage
output voltage
ambient temperature
input transition rise and fall rate
V
CC
= 1.65 V to 2.7 V
V
CC
= 2.7 V to 5.5 V
Active mode
Power-down mode; V
CC
= 0 V
Conditions
Min
1.65
0
0
0
40
-
-
Max
5.5
5.5
V
CC
5.5
+125
20
10
Unit
V
V
V
V
C
ns/V
ns/V
10. Static characteristics
Table 8.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
T
amb
=
40 C
to +85
C
V
IH
HIGH-level input voltage
V
CC
= 1.65 V to 1.95 V
V
CC
= 2.3 V to 2.7 V
V
CC
= 2.7 V to 3.6 V
V
CC
= 4.5 V to 5.5 V
V
IL
LOW-level input voltage
V
CC
= 1.65 V to 1.95 V
V
CC
= 2.3 V to 2.7 V
V
CC
= 2.7 V to 3.6 V
V
CC
= 4.5 V to 5.5 V
V
OH
HIGH-level output voltage V
I
= V
IH
or V
IL
I
O
=
100 A;
V
CC
= 1.65 V to 5.5 V
I
O
=
4
mA; V
CC
= 1.65 V
I
O
=
8
mA; V
CC
= 2.3 V
I
O
=
12
mA; V
CC
= 2.7 V
I
O
=
24
mA; V
CC
= 3.0 V
I
O
=
32
mA; V
CC
= 4.5 V
V
OL
LOW-level output voltage
V
I
= V
IH
or V
IL
I
O
= 100
A;
V
CC
= 1.65 V to 5.5 V
I
O
= 4 mA; V
CC
= 1.65 V
I
O
= 8 mA; V
CC
= 2.3 V
I
O
= 12 mA; V
CC
= 2.7 V
I
O
= 24 mA; V
CC
= 3.0 V
I
O
= 32 mA; V
CC
= 4.5 V
I
I
I
OFF
input leakage current
V
I
= 5.5 V or GND;
V
CC
= 0 V to 5.5 V
-
-
-
-
-
-
-
-
-
0.07
0.12
0.17
0.33
0.39
0.1
0.1
0.10
0.45
0.30
0.40
0.55
0.55
5
10
V
V
V
V
V
V
A
A
V
CC
0.1
1.2
1.9
2.2
2.3
3.8
-
1.54
2.15
2.50
2.62
4.11
-
-
-
-
-
-
V
V
V
V
V
V
0.65
V
CC
-
1.7
2.0
0.7
V
CC
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.7
0.8
0.3
V
CC
V
V
V
V
V
V
V
Conditions
Min
Typ
[1]
Max
Unit
0.35
V
CC
V
power-off leakage current V
I
or V
O
= 5.5 V; V
CC
= 0 V
74LVC2G74_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 24 December 2012
5 of 17
模拟电子
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
