19-3503; Rev 2; 2/06
KIT
ATION
EVALU
BLE
AVAILA
2.2MHz, Dual-Output Buck or Boost
Converter with POR and Power-Fail Output
General Description
Features
♦
4.5V to 5.5V or 5.5V to 23V Input Supply Voltage
Range
♦
0.8V (Buck) to 28V (Boost) Output Voltage
♦
Two Independent Output DC-DC Converters with
Internal Power MOSFETs
♦
Each Output can be Configured in Buck or Boost
Mode
♦
I
OUT1
and I
OUT2
of 2A and 1A (Respectively) in
Buck Mode
♦
180° Out-of-Phase Operation
♦
Clock Output for Four-Phase Operation
♦
Switching Frequency Programmable from 200kHz
to 2.2MHz
♦
Digital Soft-Start and Independent Converter
Shutdown
♦
SYNC Input, Power-On Reset, Manual Reset, And
Power-Fail Output
♦
Short-Circuit Protection (Buck)/Maximum Duty-
Cycle Limit (Boost)
♦
Thermal Shutdown
♦
Thermally Enhanced 32-Pin Thin QFN Package
Dissipates up to 2.7W at +70°C
MAX5072
The MAX5072 is a dual-output DC-DC converter with inte-
grated high-side n-channel power MOSFETs. Each output
can be configured either as a buck converter or a boost
converter. The MAX5072 is designed to manage the
power requirements of xDSL modems. The wide 5.5V to
23V input voltage range allows for the use of inexpensive
AC adapters to power the device in xDSL modem appli-
cations. Each output is programmable down to 0.8V in the
buck mode and up to 28V in the boost mode with an out-
put voltage accuracy of ±1%. In the buck mode, convert-
er 1 and converter 2 can deliver 2A and 1A, respectively.
The output switching frequency of each converter can be
programmed from 200kHz to 2.2MHz to avoid harmonics
in the xDSL frequency band of operation. Each output
operates 180° out-of-phase, thus reducing input-capaci-
tor ripple current, size, and cost. A SYNC input facilitates
external frequency synchronization. Moreover, a CLKOUT
output provides out-of-phase clock signal with respect to
converter 2, allowing four-phase operation using two
MAX5072 ICs in master-slave configuration.
The MAX5072 includes an internal digital soft-start that
reduces inrush current, eliminates output-voltage over-
shoot, and ensures monotonic rise in output voltage dur-
ing power-up. The device includes a power-good output
and power-on reset as well as manual reset. In addition,
each converter output can be shut down individually. The
MAX5072 features a "dying gasp" output, which goes low
when the input voltage drops below a preprogrammed
voltage. Protection features include output short-circuit
protection for buck mode and maximum duty-cycle limit
for boost operation, as well as thermal shutdown.
The MAX5072 is available in a thermally enhanced 32-pin
thin QFN package that can dissipate 2.7W at +70°C ambi-
ent temperature. The device is rated for operation over the
-40°C to +85°C extended, or -40°C to +125°C automotive
temperature range.
Pin Configuration
BST1/VDD1
DRAIN1
FSEL1
EN1
24
PGOOD1
SOURCE1
SOURCE1
PGND
SGND
23
22
21
20
19
18
17
16
15
14
13
MR
BYPASS
VL
VL
V+
OSC
PFI
SYNC
25
26
27
28
29
30
31
32
1
CLKOUT
Applications
xDSL Modems
xDSL Routers
Point-of-Load DC-DC Converters
MAX5072
RST
TOP VIEW
DRAIN1
COMP1
FB1
12
11
10
9
Ordering Information
PART
MAX5072ETJ
TEMP RANGE
-40°C to +85°C
PIN-PACKAGE
PKG
CODE
PGND
SOURCE2
SOURCE2
32 Thin QFN-EP*
T3255-4
(5mm x 5mm)
2
BST2/VDD2
3
DRAIN2
4
DRAIN2
5
EN2
6
FB2
7
COMP2
8
PFO
*EP
= Exposed pad.
Ordering Information continued at end of data sheet.
THIN QFN
________________________________________________________________
Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
2.2MHz, Dual-Output Buck or Boost
Converter with POR and Power-Fail Output
MAX5072
ABSOLUTE MAXIMUM RATINGS
V+ to PGND............................................................-0.3V to +25V
SGND to PGND .....................................................-0.3V to +0.3V
VL to SGND...................-0.3V to the lower of +6V or (V+ + 0.3V)
BST1/VDD1, BST2/VDD2, DRAIN_, PFO,
RST,
PGOOD1 to
SGND .................................................................-0.3V to +30V
BST1/VDD1 to SOURCE1,
BST2/VDD2 to SOURCE2 ....................................-0.3V to +6V
SOURCE_ to SGND................................................-0.6V to +25V
EN_ to SGND ................................................-0.3V to (VL + 0.3V)
CLKOUT, BYPASS, OSC, FSEL1, COMP1,
COMP2, PFI, MR, SYNC, FB_ to SGND....-0.3V to (VL + 0.3V)
SOURCE1, DRAIN1 Peak Current ..............................5A for 1ms
SOURCE2, DRAIN2 Peak Current ..............................3A for 1ms
VL, BYPASS to SGND Short Circuit............................Continuous
Continuous Power Dissipation (T
A
= +70°C)
32-Pin Thin QFN (derate 21.3mW/°C above +70°C).....2758mW*
Package Junction-to-Case Thermal Resistance (θJ
C
).......2°C/W
Operating Temperature Ranges:
MAX5072ETJ (T
MIN
to T
MAX
)...........................-40°C to +85°C
MAX5072ATJ (T
MIN
to T
MAX
).........................-40°C to +125°C
Junction Temperature ......................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
*As
per JEDEC51 standard.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V+ = VL = 5.2V or V+ = 5.5V to 23V, EN_ = VL, SYNC = GND, I
VL
= 0, PGND = SGND, C
BYPASS
= 0.22µF, C
VL
= 4.7µF (ceramic),
R
OSC
= 10kΩ (circuit of Figure 1), T
A
= T
J
= T
MIN
to T
MAX
, unless otherwise noted.) (Note 1)
PARAMETER
SYSTEM SPECIFICATIONS
Input Voltage Range
Operating Supply Current
V+
I
Q
(Note 2)
VL = V+
VL unloaded, no switching,
V
FB_
= 1V, V+ = 12V, R
OSC
= 60kΩ
EN_ = 0,
MR,
PFO, and PGOOD_ floating,
V+ = 12V, R
OSC
= 60kΩ
(MAX5072ETJ)
EN_ = 0,
MR,
PFO, and PGOOD_ floating,
V+ = 12V, R
OSC
= 60kΩ
(MAX5072ATJ)
V
OUT1
= 3.3V at 1.5A,
V
OUT2
= 2.5V at 0.75A
(f
SW
= 1.25MHz)
V+ = VL = 5V
V+ = 12V
V+ = 16V
5.5
4.5
2.2
0.6
0.6
82
80
78
%
23
5.5
1.2
1.4
mA
1.4
V
mA
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
V+ Standby Supply Current
I
STBY
Efficiency
STARTUP/VL REGULATOR
VL Undervoltage Lockout Trip
Level
VL Undervoltage Lockout
Hysteresis
VL Output Voltage
BYPASS OUTPUT
BYPASS Voltage
BYPASS Load Regulation
SOFT-START
Digital Ramp Period
Soft-Start Steps
η
UVLO
VL falling
3.95
4.1
175
4.25
V
mV
VL
V+ = 5.5V to 23V, I
SOURCE
= 0 to 40mA
I
BYPASS
= 0, R
OSC
= 60kΩ
(MAX5072ETJ)
I
BYPASS
= 0, R
OSC
= 60kΩ
(MAX5072ATJ)
0
≤
I
BYPASS
≤
50µA, R
OSC
= 60kΩ
4.9
1.98
1.975
0
5.2
2.00
2.00
2
5.5
2.02
2.025
10
V
V
BYPASS
∆V
BYPASS
V
mV
f
OSC
clock
cycles
steps
Internal 6-bit DAC
2048
64
2
_______________________________________________________________________________________
2.2MHz, Dual-Output Buck or Boost
Converter with POR and Power-Fail Output
ELECTRICAL CHARACTERISTICS (continued)
(V+ = VL = 5.2V or V+ = 5.5V to 23V, EN_ = VL, SYNC = GND, I
VL
= 0, PGND = SGND, C
BYPASS
= 0.22µF, C
VL
= 4.7µF (ceramic),
R
OSC
= 10kΩ (circuit of Figure 1), T
A
= T
J
= T
MIN
to T
MAX
, unless otherwise noted.) (Note 1)
PARAMETER
VOLTAGE-ERROR AMPLIFIER
FB_ Input Bias Current
FB_ Input Voltage Set Point
I
FB
0°C
≤
T
A
≤
+70°C
-40°C
≤
T
A
≤
+85°C
-40°C
≤
T
J
≤
+125°C (MAX5072ATJ only)
0°C to +85°C
FB_ to COMP_
Transconductance
INTERNAL MOSFETS
I
SWITCH
= 100mA,
V
BST1/VDD1
to V
SOURCE1
= 5.2V
(MAX5072ETJ)
I
SWITCH
= 100mA,
V
BST1/VDD1
to V
SOURCE1
= 5.2V
(MAX5072ATJ)
R
ON1
I
SWITCH
= 100mA,
V
BST1/VDD1
to V
SOURCE1
= 4.5V
(MAX5072ETJ)
I
SWITCH
= 100mA,
V
BST1/VDD1
to V
SOURCE1
= 4.5V
(MAX5072ATJ)
I
SWITCH
= 100mA,
V
BST2/VDD2
to V
SOURCE2
= 5.2V
I
SWITCH
= 100mA,
V
BST2/VDD2
to V
SOURCE2
= 4.5V
V
OUT1
= 3.3V, V+ = 12V (Note 3)
V
OUT2
= 2.5V, V+ = 12V (Note 3)
EN1 = 0V, V
DS
= 23V
EN2 = 0V, V
DS
= 23V
195
290
g
M
-40°C to +85°C
-40°C to +125°C (MAX5072ATJ only)
0.792
0.788
0.788
1.25
1.2
1.2
0.8
0.8
0.8
2.00
2.0
2.0
250
0.808
0.812
0.812
2.70
2.9
2.9
mS
V
nA
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
MAX5072
195
330
mΩ
On-Resistance Converter 1
200
315
200
350
330
350
2
1
630
mΩ
690
A
A
10
10
µA
µA
On-Resistance Converter 2
R
ON2
Minimum Converter 1 Output
Current
Minimum Converter 2 Output
Current
Converter 1 MOSFET Leakage
Current
Converter 2 MOSFET Leakage
Current
I
OUT1
I
OUT2
I
LK1
I
LK2
INTERNAL SWITCH CURRENT LIMIT
Current-Limit Converter 1
Current-Limit Converter 2
I
CL1
I
CL2
V+ = 12V (MAX5072ETJ)
V+ = 12V (MAX5072ATJ)
MAX5072ETJ
MAX5072ATJ
2.3
2.3
1.38
1.38
3
3
1.8
1.8
4.3
4.6
2.10
2.10
A
A
_______________________________________________________________________________________
3
2.2MHz, Dual-Output Buck or Boost
Converter with POR and Power-Fail Output
MAX5072
ELECTRICAL CHARACTERISTICS (continued)
(V+ = VL = 5.2V or V+ = 5.5V to 23V, EN_ = VL, SYNC = GND, I
VL
= 0, PGND = SGND, C
BYPASS
= 0.22µF, C
VL
= 4.7µF (ceramic),
R
OSC
= 10kΩ (circuit of Figure 1), T
A
= T
J
= T
MIN
to T
MAX
, unless otherwise noted.) (Note 1)
PARAMETER
INTERNAL OSCILLATOR/SYNC
Maximum Duty Cycle
Switching Frequency Range
Switching Frequency
Switching Frequency Accuracy
SYNC Frequency Range
SYNC High Threshold
SYNC Low Threshold
SYNC Input MIN Pulse Width
Clock Output Phase Delay
SYNC to SOURCE 1 Phase Delay
Clock Output High Level
Clock Output Low Level
FSEL1
FSEL1 Input High Threshold
FSEL1 Input Low Threshold
EN_ INPUTS
EN_ Input High Threshold
EN_ Input Low Threshold
EN_ Bias Current
MR
Minimum Pulse Width
MR
Glitch Immunity
MR
to
RST
Propagation Delay
MR
Input High Threshold
MR
Input Low Threshold
MR
Internal Pullup Resistor
Power-On-Reset Threshold
FB_ to
RST
Propagation Delay
RST
Active Timeout Period
RST
Output Voltage
RST
Output Leakage Current
t
MD
V
IH
V
IL
R
MR
V
TH
t
FD
t
RP
V
RST_
I
RSTLK
I
SINK
= 3mA (MAX5072ETJ)
I
SINK
= 3mA (MAX5072ATJ)
V+ = VL = 5.2V, V
RST
= 23V, V
FB
_ = 0.8V
V
IH
V
IL
I
B(EN)
t
MR
Maximum glitch pulse width allowed for
RST
to remain high
V+ = VL = +5.2V
V+ = VL = +5.2V
RST
goes high 180ms after V
OUT1
and
V
OUT2
cross this threshold
FB overdrive from 0.8V to 0.6V
140
2.4
0.8
44
90
92.5
1.1
200
360
0.4
0.52
1
95
100
1
V+ = VL = +5.2V
V+ = VL = +5.2V
2.4
1.8
1.2
0.8
250
10
V
V
nA
µs
ns
µs
V
V
kΩ
% V
OUT
µs
ms
V
µA
f
SYNC
V
SYNCH
V
SYNCL
t
SYNCIN
CLKOUT
PHASE
V
CLKOUTH
V
CLKOUTL
V
IH
V
IL
ROSC = 60kΩ, 1%, with respect to
converter 2/SOURCE2 waveform
VL = 5.2V, sourcing 5mA
VL = 5.2V, sinking 5mA
V+ = VL = +5.2V
V+ = VL = +5.2V
2.4
0.8
4
0.4
100
45
45
D
MAX
f
SW
f
SET
SYNC = SGND, f
SW
= 1.25MHz
SYNC = SGND, f
SW
= 2.2MHz
Each converter
R
OSC
= 10kΩ, each converter
5.6kΩ
≤
R
OSC
≤
56kΩ, 1%, each converter
SYNC input frequency is twice the
individual converter frequency
84
84
200
1125
-15
400
2.4
0.8
1250
86
86
95
95
2200
1375
+15
4400
%
kHz
kHz
%
kHz
V
V
ns
degrees
degrees
V
V
V
V
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SYNC
PHASE
ROSC = 60kΩ, 1%
MANUAL RESET (MR) AND POWER-ON-RESET (RST)
4
_______________________________________________________________________________________
2.2MHz, Dual-Output Buck or Boost
Converter with POR and Power-Fail Output
ELECTRICAL CHARACTERISTICS (continued)
(V+ = VL = 5.2V or V+ = 5.5V to 23V, EN_ = VL, SYNC = GND, I
VL
= 0, PGND = SGND, C
BYPASS
= 0.22µF, C
VL
= 4.7µF (ceramic),
R
OSC
= 10kΩ (circuit of Figure 1), T
A
= T
J
= T
MIN
to T
MAX
, unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
PGOOD1 goes high after V
OUT
crosses
PGOOD1 threshold
I
SINK
= 3mA (MAX5072ETJ)
I
SINK
= 3mA (MAX5072ATJ)
V+ = VL = 5.2V, V
PGOOD1
= 23V, V
FB1
= 1V
PFI falling
V
PFI
= 0.75V
100mV overdrive
t
PFD
V
PFO
I
LKPFO
T
SHDN
T
HYST
50mV overdrive
I
SINK
= 3mA (MAX5072ETJ)
I
SINK
= 3mA (MAX5072ATJ)
V+ = VL = 5.2V, V
PFO
= 5.5V, V
PFI
= 1V
Junction temperature
Junction temperature
+150
30
35
35
0.4
0.52
1
0.76
0.78
20
MIN
TYP
MAX
UNITS
POWER-GOOD OUTPUT (PGOOD1)
PGOOD1 Threshold
PGOOD1 Output Voltage
PGOOD1 Output Leakage Current
PFI Trip Level
PFI Hysteresis
PFI Input Bias Current
PFI Glitch Immunity
PFI to PFO Propagation Delay
PFO Output Low Voltage
PFO Output Leakage Current
THERMAL MANAGEMENT
Thermal Shutdown
Thermal Hysteresis
PGOOD1VTH
MAX5072
90
92.5
95
0.4
0.52
1
0.80
500
% V
OUT
V
µA
V
mV
nA
µs
µs
V
µA
°C
°C
V
PGOOD1
I
LKPGOOD1
V
TH
V
THH
I
B(PFI)
DYING GASP POWER-FAIL INPUT (PFI), POWER-FAIL OUTPUT (PFO)
Note 1:
Specifications at -40°C are guaranteed by design and not production tested.
Note 2:
Operating supply range (V+) is guaranteed by VL line regulation test. Connect V+ to VL for 5V operation.
Note 3:
Output current may be limited by the power dissipation of the package, see the
Power Dissipation
section in the
Applications Information.
_______________________________________________________________________________________
5
DSP 与 ARM 处理器
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
