• Ultra-Low On-Resistance Critical for Application
• Low Thermal Resistance PowerPAK
®
Package
with Low 1.07 mm Profile
• 100 % R
g
and Avalanche Tested
• Compliant to RoHS Directive 2002/95/EC
PowerPAK SO-8
6.15 mm
S
1
2
3
S
S
5.15 mm
APPLICATIONS
• Active Clamp in Intermediate DC/DC Power Supplies
S
G
4
D
8
7
6
5
D
D
D
G
Bottom View
Ordering Information:
Si7439DP-T1-E3 (Lead (Pb)-free)
Si7439DP-T1-GE3 (Lead (Pb)-free and Halogen-free)
D
P-Channel MOSFET
ABSOLUTE MAXIMUM RATINGS
(T
A
= 25 °C, unless otherwise noted)
Parameter
Drain-Source Voltage
Gate-Source Voltage
Continuous Drain Current (T
J
= 150 °C)
a
Pulsed Drain Current
Continuous Source Current (Diode Conduction)
a
Single Pulse Avalanche Current
Single Pulse Avalanche Energy
Maximum Power Dissipation
a
Operating Junction and Storage Temperature Range
Soldering Recommendations (Peak Temperature)
b, c
L = 0.1 mH
T
A
= 25 °C
T
A
= 70 °C
T
A
= 25 °C
T
A
= 70 °C
Symbol
V
DS
V
GS
I
D
I
DM
I
S
I
AS
E
AS
P
D
T
J
, T
stg
5.4
3.4
- 55 to 150
260
- 4.2
- 40
80
1.9
1.2
mJ
W
°C
- 5.2
- 4.1
- 50
- 1.6
10 s
Steady State
- 150
± 20
- 3.0
- 2.4
A
Unit
V
THERMAL RESISTANCE RATINGS
Parameter
Maximum Junction-to-Ambient
a
Maximum Junction-to-Case (Drain)
t
10 s
Steady State
Steady State
Symbol
R
thJA
R
thJC
Typical
18
50
1.0
Maximum
23
65
1.5
°C/W
Unit
Notes:
a. Surface mounted on 1" x 1" FR4 board.
b. See solder profile (www.vishay.com/ppg?73257). The PowerPAK SO-8 is a leadless package. The end of the lead terminal is exposed copper
(not plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed and is not
required to ensure adequate bottom side solder interconnection.
c. Rework conditions: manual soldering with a soldering iron is not recommended for leadless components.
Document Number: 73106
S10-2246-Rev. E, 04-Oct-10
www.vishay.com
1
Si7439DP
Vishay Siliconix
SPECIFICATIONS
(T
J
= 25 °C, unless otherwise noted)
Parameter
Static
Gate Threshold Voltage
Gate-Body Leakage
Zero Gate Voltage Drain Current
On-State Drain Current
a
Drain-Source On-State Resistance
a
Forward Transconductance
a
Diode Forward Voltage
a
Dynamic
b
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
Gate Resistance
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Source-Drain Reverse Recovery Time
Q
g
Q
gs
Q
gd
R
g
t
d(on)
t
r
t
d(off)
t
f
t
rr
I
F
= - 2.9 A, dI/dt = 100 A/µs
V
DD
= - 75 V, R
L
= 15.5
I
D
- 4.8 A, V
GEN
= - 10 V, R
G
= 6
1.5
V
DS
= - 75 V, V
GS
= - 10 V, I
D
= - 5.2 A
88
17.5
26.5
3
25
46
115
64
100
4.5
40
70
180
100
150
ns
135
nC
V
GS(th)
I
GSS
I
DSS
I
D(on)
R
DS(on)
g
fs
V
SD
V
DS
= V
GS
, I
D
= - 250 µA
V
DS
= 0 V, V
GS
= ± 20 V
V
DS
= - 150 V, V
GS
= 0 V
V
DS
= - 150 V, V
GS
= 0 V, T
J
= 70 °C
V
DS
½-
10 V, V
GS
= - 10 V
V
GS
= - 10 V, I
D
= - 5.2 A
V
GS
= - 6 V, I
D
= - 5.0 A
V
DS
= - 15 V, I
D
= - 5.2 A
I
S
= - 4.2 A, V
GS
= 0 V
- 30
0.073
0.077
19
- 0.78
- 1.2
0.090
0.095
- 2.0
- 4.0
± 100
-1
- 10
V
nA
µA
A
S
V
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
Notes:
a. Pulse test; pulse width
300 µs, duty cycle
2 %.
b. Guaranteed by design, not subject to production testing.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
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