SU5642885D8N0CU
June 27, 2006
Ordering Information
Part Numbers
SM5642885D8N0CL
SX5642885D8N0CL
Description
128Mx64 (1GB), DDR, 184-pin DIMM, Unbuffered, Non-ECC,
64Mx8 Based, DDR333B, 31.75mm, 22Ω DQ termination.
128Mx64 (1GB), DDR, 184-pin DIMM, Unbuffered, Non-ECC,
64Mx8 Based, DDR333B, 31.75mm, 22Ω DQ termination,
Mixed Process Module.
128Mx64 (1GB), DDR, 184-pin DIMM, Unbuffered, Non-ECC,
64Mx8 Based, DDR333B, 31.75mm, 22Ω DQ termination,
Green Module (RoHS Compliant).
128Mx64 (1GB), DDR, 184-pin DIMM, Unbuffered, Non-ECC,
64Mx8 Based, DDR266A, 31.75mm, 22Ω DQ termination,
Green Module (RoHS Compliant).
128Mx64 (1GB), DDR, 184-pin DIMM, Unbuffered, Non-ECC,
64Mx8 Based, DDR266B, 31.75mm, 22Ω DQ termination,
Green Module (RoHS Compliant).
Module Speed
PC2700 @ CL 2.5
PC2700 @ CL 2.5
SG5642885D8N0CL
PC2700 @ CL 2.5
SG5642885D8N0CG
PC2100 @ CL 2.0, 2.5
SG5642885D8N0CH
PC2100 @ CL 2.5
Corporate Headquarters:
P. O. Box 1757, Fremont, CA 94538, USA • Tel:(510) 623-1231 • Fax:(510) 623-1434 • E-mail: info@smartm.com
Europe:
5 Kelvin Park South, Kelvin South, East Kilbride, G75 ORH, United Kingdom • Tel: +44-870-870-8747 • Fax: +44-870-870-8757
Asia/Pacific:
Plot 18, Lrg Jelawat 4, Kawasan Perindustrian Seberang Jaya 13700, Prai, Penang, Malaysia • Tel: +604-3992909 • Fax: +604-3992903
1
SU5642885D8N0CU
June 27, 2006
Revision History
• June 27, 2006
Changed the datasheet part number from SU5642885D8N0CL to SU5642885D8N0CU because of the addition
of new Module Speeds.
Added SG5642885D8N0CG & SG5642885D8N0CH to the datasheet to represent the new Module Speeds.
Obsoleted SB5646485D8N0CL from the Ordering Information on page 1 because the Module Process Technol-
ogy is no longer supported.
Added termination resistors to the Address and Control lines on page 5.
Corrected the notes under the IDD power table on page 16.
• September 2, 2004
Datasheet released.
Corporate Headquarters:
P. O. Box 1757, Fremont, CA 94538, USA • Tel:(510) 623-1231 • Fax:(510) 623-1434 • E-mail: info@smartm.com
Europe:
5 Kelvin Park South, Kelvin South, East Kilbride, G75 ORH, United Kingdom • Tel: +44-870-870-8747 • Fax: +44-870-870-8757
Asia/Pacific:
Plot 18, Lrg Jelawat 4, Kawasan Perindustrian Seberang Jaya 13700, Prai, Penang, Malaysia • Tel: +604-3992909 • Fax: +604-3992903
2
SU5642885D8N0CU
June 27, 2006
1GByte (128Mx64) DDR SDRAM Module - 64Mx8 Based
184-pin DIMM, Unbuffered, Non-ECC
Features
• Standard
• Configuration
• Cycle Time
•
•
•
•
:
:
:
JEDEC
Non-ECC
6.0ns (PC2700)
7.5ns (PC2100)
2.0, 2.5
2, 4, 8
Sequential/Interleave
4
•
•
•
•
•
•
•
Operating Voltage :
2.5V
Refresh
:
8K/64ms
Device Physicals :
400mil TSOP
Lead Finish
:
Gold
Length x Height
:
133.35mm x 31.75mm
No. of sides
:
Double-sided
Mating Connector (Examples)
Vertical
:
AMP - 5390241-1
CAS# Latency
:
Burst Length
:
Burst Type
:
No. of Internal
Banks per SDRAM :
184-pin DDR DIMM Pin List
Pin Pin
No. Name
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
V
REF
DQ0
V
SS
DQ1
DQS0
DQ2
V
DD
DQ3
NC
NC
V
SS
DQ8
DQ9
DQS1
V
DDQ
CK1
CK1#
V
SS
DQ10
DQ11
CKE0
V
DDQ
DQ16
Pin Pin
No. Name
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
DQ17
DQS2
V
SS
A9
DQ18
A7
V
DDQ
DQ19
A5
DQ24
V
SS
DQ25
DQS3
A4
V
DD
DQ26
DQ27
A2
V
SS
A1
NC
NC
V
DD
Pin Pin
No. Name
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
NC
A0
NC
V
SS
NC
BA1
DQ32
V
DDQ
DQ33
DQS4
DQ34
V
SS
BA0
DQ35
DQ40
V
DDQ
WE#
DQ41
CAS#
V
SS
DQS5
DQ42
DQ43
Pin Pin
No. Name
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
V
DD
NC
DQ48
DQ49
V
SS
CK2#
CK2
V
DDQ
DQS6
DQ50
DQ51
V
SS
V
DDID
DQ56
DQ57
V
DD
DQS7
DQ58
DQ59
V
SS
NC
SDA
SCL
Pin
No.
93
94
95
96
97
98
99
Pin
Name
V
SS
DQ4
DQ5
V
DDQ
DM0
DQ6
DQ7
Pin
No.
Pin
Name
Pin Pin
No. Name
139 V
SS
140 NC
141 A10
142 NC
143 V
DDQ
144 NC
145 V
SS
146 DQ36
147 DQ37
148 V
DD
149 DM4
150 DQ38
151 DQ39
152 V
SS
153 DQ44
154 RAS#
155 DQ45
156 V
DDQ
157 CS0#
158 CS1#
159 DM5
160 V
SS
161 DQ46
Pin Pin
No. Name
162 DQ47
163 NC
164 V
DDQ
165 DQ52
166 DQ53
167 NC
168 V
DD
169 DM6
170 DQ54
171 DQ55
172 V
DDQ
173 NC
174 DQ60
175 DQ61
176 V
SS
177 DM7
178 DQ62
179 DQ63
180 V
DDQ
181 SA0
182 SA1
183 SA2
184 V
DDSPD
116 V
SS
117 DQ21
118 A11
119 DM2
120 V
DD
121 DQ22
122 A8
123 DQ23
124 V
SS
125 A6
126 DQ28
127 DQ29
128 V
DDQ
129 DM3
130 A3
131 DQ30
132 V
SS
133 DQ31
134 NC
135 NC
136 V
DDQ
137 CK0
138 CK0#
100 V
SS
101 NC
102 NC
103 NC
104 V
DDQ
105 DQ12
106 DQ13
107 DM1
108 V
DD
109 DQ14
110 DQ15
111
CKE1
112 V
DDQ
113 NC
114 DQ20
115 A12
(All specifications of this module are subject to change without notice.)
Corporate Headquarters:
P. O. Box 1757, Fremont, CA 94538, USA • Tel:(510) 623-1231 • Fax:(510) 623-1434 • E-mail: info@smartm.com
Europe:
5 Kelvin Park South, Kelvin South, East Kilbride, G75 ORH, United Kingdom • Tel: +44-870-870-8747 • Fax: +44-870-870-8757
Asia/Pacific:
Plot 18, Lrg Jelawat 4, Kawasan Perindustrian Seberang Jaya 13700, Prai, Penang, Malaysia • Tel: +604-3992909 • Fax: +604-3992903
3
SU5642885D8N0CU
June 27, 2006
Pin Description Table
Symbol
CK0, CK0#
CK1, CK1#
CK2, CK2#
CKE0, CKE1
CS0#, CS1#
RAS#, CAS#,
WE#
BA0, BA1
A0~A9,
A10/AP,
A11~A12
Type
SSTL
Polarity
Crossing
Point
Active High
Active Low
Active Low
-
-
Function
The system clock inputs. All address and command lines are sampled on the cross point of the
rising edge of CK and falling edge of CK#. A Delay Locked Loop (DLL) circuit is driven from the
clock inputs and output timing for read operations is synchronized to the input clock.
Activates the SDRAM CK signal when high and deactivates the CK signal when low. By deacti-
vating the clocks, CKE low initiates the Power Down mode, or the Self Refresh mode.
Enables the associated DDR SDRAM command decoder when low and disables decoder when
high. When decoder is disabled, new commands are ignored but previous operations continue.
When sampled at the positive rising edge of the clock, CAS#, RAS#, and WE# define the oper-
ations to be executed by the SDRAM.
Selects which of the four internal SDRAM banks is activated.
During a Bank Activate command cycle, A0-A12 defines the row address (RA0-RA12) when
sampled at the rising clock edge.
During a Read or Write command cycle, A0-A9, A11 defines the column address (CA0-CA9,
CA11) when sampled at the rising clock edge. In addition to the column address, A10/AP is
used to invoke autoprecharge operation at the end of the burst read or write cycle. If A10/AP is
high, autoprecharge is selected and BA0, BA1 defines the bank to be precharged. If AP is low,
autoprecharge is disabled.
During a Precharge command cycle, A10/AP is used in conjunction with BA0, BA1 to control
which bank(s) to precharge. If AP is high, all banks will be precharged regardless of the state of
BA0 or BA1. If AP is low, BA0 and BA1 are used to define which bank to precharge.
Data Input/Output pins.
Masks write data when high, issued concurrently with input data. Both DM and DQ have a write
latency of one clock once the write command is registered into the SDRAM.
Data strobe for input and output data.
SSTL
SSTL
SSTL
SSTL
SSTL
DQ0~DQ63
DM0~DM7
DQS0~DQS7
SSTL
SSTL
SSTL
-
Active High
Negative &
Positive
Edge
-
-
-
-
-
-
-
-
-
SA0~SA2
SDA
SCL
V
DD,
V
SS
V
REF
V
DDQ
V
DDSPD
V
DDID
NC
LVTTL
LVTTL
LVTTL
Supply
Supply
Supply
Supply
Supply
-
These signals are tied on the system to either V
SS
or V
DD
to configure the serial SPD.
This bidirectional pin is used to transfer data into or out of the SPD EEPROM. A resistor must
be connected on the system board from the SDA bus line to V
DD
to act as a pullup.
This signal is used to clock data into and out of the SPD EEPROM. A resistor may be con-
nected on the system board from the SCL bus line to V
DD
to act as a pullup.
Power and ground for the DDR SDRAM input buffers and core logic.
Reference voltage for SSTL2 inputs.
Isolated power supply for the DDR SDRAM output buffers to provide improved noise immunity.
Serial EEPROM positive power supply (wired to a separate power pin at the connector which
supports both 2.3 Volt and 3.3 Volt operation).
V
DD
Indentification Flag.
No Connect.
Corporate Headquarters:
P. O. Box 1757, Fremont, CA 94538, USA • Tel:(510) 623-1231 • Fax:(510) 623-1434 • E-mail: info@smartm.com
Europe:
5 Kelvin Park South, Kelvin South, East Kilbride, G75 ORH, United Kingdom • Tel: +44-870-870-8747 • Fax: +44-870-870-8757
Asia/Pacific:
Plot 18, Lrg Jelawat 4, Kawasan Perindustrian Seberang Jaya 13700, Prai, Penang, Malaysia • Tel: +604-3992909 • Fax: +604-3992903
4
SU5642885D8N0CU
June 27, 2006
Block Diagram
CS0#
CS1#
CKE0
CKE1
DQS0
DM0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
22Ω
22Ω
22Ω
22Ω
22Ω
22Ω
22Ω
22Ω
22Ω
22Ω
S#
DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
S#
DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
S#
DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
S#
DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CKE
U1
S#
DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
S#
DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
S#
DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
S#
DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CKE
DQS4
DM4
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
U10
22Ω
22Ω
22Ω
22Ω
22Ω
22Ω
22Ω
22Ω
22Ω
22Ω
S#
DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
S#
DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
S#
DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
S#
DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CKE
U5
S#
DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
S#
DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
S#
DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
S#
DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CKE
U14
DQS1
DM1
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
22Ω
22Ω
22Ω
22Ω
22Ω
22Ω
22Ω
22Ω
22Ω
22Ω
CKE
CKE
DQS5
DM5
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
U2
U11
22Ω
22Ω
22Ω
22Ω
22Ω
22Ω
22Ω
22Ω
22Ω
22Ω
CKE
CKE
U6
U15
DQS2
DM2
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
22Ω
22Ω
22Ω
22Ω
22Ω
22Ω
22Ω
22Ω
22Ω
22Ω
CKE
CKE
DQS6
DM6
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
U3
U12
22Ω
22Ω
22Ω
22Ω
22Ω
22Ω
22Ω
22Ω
22Ω
22Ω
CKE
CKE
U7
U16
DQS3
DM3
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
22Ω
22Ω
22Ω
22Ω
22Ω
22Ω
22Ω
22Ω
22Ω
22Ω
CKE
CKE
DQS7
DM7
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
U4
U13
22Ω
22Ω
22Ω
22Ω
22Ω
22Ω
22Ω
22Ω
22Ω
22Ω
CKE
CKE
U8
U17
3Ω
SPD
EEPROM
SA0
V
DD
SA1
SA2 U20
SCL
SDA
WP
A0~A12
BA0, BA1
RAS#
CAS#
WE#
CS0#
CS1#
CKE0
CKE1
to all devices (U1~U8, U10~U17)
to all devices (U1~U8, U10~U17)
to all devices (U1~U8, U10~U17)
to all devices (U1~U8, U10~U17)
to all devices (U1~U8, U10~U17)
to devices (U1~U8)
to devices (U10~U17)
to devices (U1~U8)
to devices (U10~U18)
SA0
SA1
SA2
SCL
SDA
V
DDSPD
Corporate Headquarters:
P. O. Box 1757, Fremont, CA 94538, USA • Tel:(510) 623-1231 • Fax:(510) 623-1434 • E-mail: info@smartm.com
Europe:
5 Kelvin Park South, Kelvin South, East Kilbride, G75 ORH, United Kingdom • Tel: +44-870-870-8747 • Fax: +44-870-870-8757
Asia/Pacific:
Plot 18, Lrg Jelawat 4, Kawasan Perindustrian Seberang Jaya 13700, Prai, Penang, Malaysia • Tel: +604-3992909 • Fax: +604-3992903
5
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