SiHA12N50E
www.vishay.com
Vishay Siliconix
E Series Power MOSFET
FEATURES
Thin-Lead TO-220 FULLPAK
D
• Low figure-of-merit (FOM) R
on
x Q
g
•
•
•
•
•
Low input capacitance (C
iss
)
Reduced switching and conduction losses
Low gate charge (Q
g
)
Available
Avalanche energy rated (UIS)
Material categorization: for definitions of compliance
please see
www.vishay.com/doc?99912
G
GD
S
S
N-Channel MOSFET
APPLICATIONS
• Computing
- PC silver box / ATX power supplies
• Lighting
- Two stage LED lighting
• Consumer electronics
• Applications using hard switched topologies
- Power factor correction (PFC)
- Two switch forward converter
- Flyback converter
• Switch mode power supplies (SMPS)
PRODUCT SUMMARY
V
DS
(V) at T
J
max.
R
DS(on)
max. () at 25 °C
Q
g
max. (nC)
Q
gs
(nC)
Q
gd
(nC)
Configuration
V
GS
= 10 V
50
6
10
Single
550
0.380
ORDERING INFORMATION
Package
Lead (Pb)-free
Lead (Pb)-free and halogen-free
Thin-Lead TO-220 FULLPAK
SiHA12N50E-E3
SiHA12N50E-GE3
ABSOLUTE MAXIMUM RATINGS
(T
C
= 25 °C, unless otherwise noted)
PARAMETER
Drain-source voltage
Gate-source voltage
Continuous drain current (T
J
= 150 °C)
e
Pulsed drain
current
a
energy
b
V
GS
at 10 V
T
C
= 25 °C
T
C
= 100 °C
SYMBOL
V
DS
V
GS
I
D
I
DM
E
AS
P
D
T
J
, T
stg
V
DS
= 0 V to 80 % V
DS
for 10 s
M3 screw
dV/dt
LIMIT
500
± 30
10.5
6.6
21
0.91
103
32
-55 to +150
70
27
300
0.6
W/°C
mJ
W
°C
V/ns
°C
Nm
A
UNIT
V
Linear derating factor
Single pulse avalanche
Maximum power dissipation
Operating junction and storage temperature range
Drain-source voltage slope
Reverse diode dV/dt
d
Soldering recommendations (peak temperature)
c
Mounting torque
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature
b. V
DD
= 50 V, starting T
J
= 25 °C, L = 28.2 mH, R
g
= 25
,
I
AS
= 2.7 A
c. 1.6 mm from case
d. I
SD
I
D
, dI/dt = 100 A/μs, starting T
J
= 25 °C
e. Limited by maximum junction temperature
S17-1307-Rev. D, 21-Aug-17
Document Number: 91637
1
For technical questions, contact:
hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
SiHA12N50E
www.vishay.com
Vishay Siliconix
THERMAL RESISTANCE RATINGS
PARAMETER
Maximum junction-to-ambient
Maximum junction-to-case (drain)
SYMBOL
R
thJA
R
thJC
TYP.
-
-
MAX.
65
3.9
UNIT
°C/W
SPECIFICATIONS
(T
J
= 25 °C, unless otherwise noted)
PARAMETER
Static
Drain-source breakdown voltage
V
DS
temperature coefficient
Gate-source threshold voltage (N)
Gate-source leakage
Zero gate voltage drain current
Drain-source on-state resistance
Forward transconductance
Dynamic
Input capacitance
Output capacitance
Reverse transfer capacitance
Effective output capacitance, energy
related
a
Effective output capacitance, time
related
b
Total gate charge
Gate-source charge
Gate-drain charge
Turn-on delay time
Rise time
Turn-off delay time
Fall time
Gate input resistance
Drain-Source Body Diode Characteristics
Continuous source-drain diode current
Pulsed diode forward current
Diode forward voltage
Reverse recovery time
Reverse recovery charge
Reverse recovery current
I
S
I
SM
V
SD
t
rr
Q
rr
I
RRM
MOSFET symbol
showing the
integral reverse
p - n junction diode
D
SYMBOL
V
DS
V
DS
/T
J
V
GS(th)
I
GSS
I
DSS
R
DS(on)
g
fs
C
iss
C
oss
C
rss
C
o(er)
TEST CONDITIONS
V
GS
= 0 V, I
D
= 250 μA
Reference to 25 °C, I
D
= 1 mA
V
DS
= V
GS
, I
D
= 250 μA
V
GS
= ± 20 V
V
GS
= ± 30 V
V
DS
= 500 V, V
GS
= 0 V
V
DS
= 400 V, V
GS
= 0 V, T
J
= 125 °C
V
GS
= 10 V
I
D
= 6 A
V
DS
= 30 V, I
D
= 6 A
MIN.
500
-
2.0
-
-
-
-
-
-
-
-
-
-
TYP.
-
0.60
-
-
-
-
-
0.330
3.1
886
52
6
45
131
25
6
10
13
16
29
12
0.92
MAX.
-
-
4.0
± 100
±1
1
10
0.380
-
-
-
-
UNIT
V
V/°C
V
nA
μA
μA
S
V
GS
= 0 V,
V
DS
= 100 V,
f = 1 MHz
pF
-
-
50
-
-
26
32
58
24
-
ns
nC
V
DS
= 0 V to 400 V, V
GS
= 0 V
C
o(tr)
Q
g
Q
gs
Q
gd
t
d(on)
t
r
t
d(off)
t
f
R
g
f = 1 MHz, open drain
V
DD
= 400 V, I
D
= 6 A,
V
GS
= 10 V, R
g
= 9.1
V
GS
= 10 V
I
D
= 6 A, V
DS
= 400 V
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
244
2.5
19
10.5
A
21
1.2
-
-
-
V
ns
μC
A
G
S
T
J
= 25 °C, I
S
= 7.5 A, V
GS
= 0 V
T
J
= 25 °C, I
F
= I
S
= 6 A,
dI/dt = 100 A/μs, V
R
= 25 V
Notes
a. C
oss(er)
is a fixed capacitance that gives the same energy as C
oss
while V
DS
is rising from 0 % to 80 % V
DSS
b. C
oss(tr)
is a fixed capacitance that gives the same charging time as C
oss
while V
DS
is rising from 0 % to 80 % V
DSS
S17-1307-Rev. D, 21-Aug-17
Document Number: 91637
2
For technical questions, contact:
hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
SiHA12N50E
www.vishay.com
TYPICAL CHARACTERISTICS
(25 °C, unless otherwise noted)
30
R
DS(on)
, Drain-to-Source On-Resistance
(Normalized)
15 V
14 V
13 V
12 V
11 V
10 V
9V
8V
7V
6V
BOTTOM 5 V
TOP
Vishay Siliconix
3.0
T
J
= 25 °C
2.5
I
D
= 6 A
I
D
, Drain-to-Source Current (A)
24
2.0
18
1.5
12
1.0
V
GS
= 10 V
0.5
6
0
0
5
10
15
20
25
V
DS
, Drain-to-Source Voltage (V)
30
0
- 60 - 40 - 20
0 20 40 60 80 100 120 140 160
T
J
, Junction Temperature (°C)
Fig. 1 - Typical Output Characteristics
20
TOP
15 V
14 V
13 V
12 V
11 V
10 V
9V
8V
7V
6V
BOTTOM 5 V
Fig. 4 - Normalized On-Resistance vs. Temperature
T
J
= 150 °C
10 000
V
GS
= 0 V, f = 1 MHz
C
iss
= C
gs
+ C
gd
, C
ds
shorted
C
rss
= C
gd
C
oss
= C
ds
+ C
gd
I
D
, Drain-to-Source Current (A)
16
1000
C, Capacitance (pF)
C
iss
12
100
C
oss
C
rss
8
4
10
0
0
5
10
15
20
25
V
DS
, Drain-to-Source Voltage (V)
30
1
0
100
200
300
400
V
DS
, Drain-to-Source Voltage (V)
500
Fig. 2 - Typical Output Characteristics
30
Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage
6
5000
T
J
= 25 °C
25
I
D
, Drain-to-Source Current (A)
5
20
C
oss
(pF)
E
oss
4
C
oss
500
2
V
DS
= 30.4 V
E
oss
(μJ)
15
T
J
= 150 °C
10
3
5
1
0
0
5
10
15
20
25
V
GS
,
Gate-to-Source
Voltage (V)
50
0
100
200
V
DS
300
400
500
0
Fig. 3 - Typical Transfer Characteristics
Fig. 6 - C
oss
and E
oss
vs. V
DS
S17-1307-Rev. D, 21-Aug-17
Document Number: 91637
3
For technical questions, contact:
hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
SiHA12N50E
www.vishay.com
Vishay Siliconix
12
24
V
DS
= 400 V
V
DS
= 250 V
V
DS
= 100 V
V
GS
,
Gate-to-Source
Voltage (V)
20
9
16
I
D
, Drain Current (A)
0
10
20
30
40
Q
g
, Total
Gate
Charge (nC)
50
12
6
8
3
4
0
0
25
50
75
100
125
T
C
, Case Temperature (°C)
150
Fig. 7 - Typical Gate Charge vs. Gate-to-Source Voltage
Fig. 10 - Maximum Drain Current vs. Case Temperature
650
V
DS
, Drain-to-Source Breakdown Voltage (V)
625
600
575
550
525
500
I
D
= 250 μA
475
- 60 - 40 - 20
0
20
40
60
80 100 120 140 160
T
J
, Junction Temperature (°C)
100
I
SD
, Reverse Drain Current (A)
T
J
= 150 °C
10
1
T
J
= 25 °C
V
GS
= 0 V
0.1
0.2
0.4
0.6
0.8
1.0
V
SD
,
Source-Drain
Voltage (V)
1.2
1.4
Fig. 8 - Typical Source-Drain Diode Forward Voltage
100
Operation in this Area
Limited by R
DS(on)
10
I
D
, Drain Current (A)
100 μs
1
Limited by R
DS(on)
*
1 ms
0.1
T
C
= 25
°C
T
J
= 150 °C
Single
Pulse
1
I
DM
Limited
Fig. 11 - Temperature vs. Drain-to-Source Voltage
10 ms
0.01
BVDSS Limited
10
100
1000
V
DS
, Drain-to-Source Voltage (V)
* V
GS
> minimum V
GS
at which R
DS(on)
is
specified
Fig. 9 - Maximum Safe Operating Area
S17-1307-Rev. D, 21-Aug-17
Document Number: 91637
4
For technical questions, contact:
hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
SiHA12N50E
www.vishay.com
Vishay Siliconix
1
Duty Cycle = 0.5
Normalized Effective Transient
Thermal Impedance
0.2
0.1
0.1
0.05
0.02
Single
Pulse
0.01
0.0001
0.001
0.01
Pulse Time (s)
0.1
1
10
Fig. 12 - Normalized Thermal Transient Impedance, Junction-to-Case
R
D
V
DS
V
GS
R
G
V
DS
t
p
V
DD
+
-
V
DD
D.U.T.
V
DS
10 V
Pulse width
≤
1 µs
Duty factor
≤
0.1 %
I
AS
Fig. 16 - Unclamped Inductive Waveforms
Fig. 13 - Switching Time Test Circuit
V
DS
90 %
10 V
Q
GS
10 %
V
GS
t
d(on)
t
r
t
d(off)
t
f
Q
G
Q
GD
V
G
Charge
Fig. 14 - Switching Time Waveforms
Fig. 17 - Basic Gate Charge Waveform
Current regulator
Same type as D.U.T.
50 kΩ
L
Vary t
p
to obtain
required I
AS
R
G
V
DS
D.U.T
I
AS
+
-
12 V
0.2 µF
0.3 µF
V
DD
+
D.U.T.
10 V
t
p
0.01
Ω
V
GS
3 mA
-
V
DS
Fig. 15 - Unclamped Inductive Test Circuit
I
G
I
D
Current sampling resistors
Fig. 18 - Gate Charge Test Circuit
S17-1307-Rev. D, 21-Aug-17
Document Number: 91637
5
For technical questions, contact:
hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
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