Operating Temperature Range .......................... -40NC to +85NC
Junction Temperature .....................................................+150NC
Storage Temperature Range............................ -65NC to +150NC
Lead Temperature (soldering, 10s) ................................+300NC
Soldering Temperature (reflow) ......................................+260NC
Note 1:
Signals on SEL, SELB, AIN_, BIN _, AOUTA_, AOUTB_, BOUTA_, and BOUTB_ exceeding V
CC
or GND are clamped by
internal diodes. Limit forward-diode current to maximum current rating.
PACKAGE THERMAL CHARACTERISTICS (Note 2)
TQFN
Junction-to-Ambient Thermal Resistance (q
JA
) ..........35°C/W
Junction-to-Case Thermal Resistance (q
JC
) .................2°C/W
Note 2:
Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-
layer board. For detailed information on package thermal considerations, refer to
www.maxim-ic.com/thermal-tutorial.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
CC
= 3.3V
Q10%,
T
A
= -40NC to +85NC
,
unless otherwise noted. Typical values are at V
CC
= 3.3V, T
A
= +25NC, unless otherwise
noted.) (Note 3)
PARAMETER
DC PERFORMANCE
Analog-Signal Range
On-Resistance
On-Resistance Match
Between Channels
On-Resistance Flatness
_OUTA_ or _OUTB_
Off-Leakage Current
V
INPUT
R
ON
DR
ON
R
FLAT(ON)
AIN_, BIN_, AOUTA_, BOUTA_, AOUTB_,
BOUTB_
V
CC
= +3.0V, I
AIN_
= I
BIN_
= 15mA,
V_
OUTA_
= V_
OUTB_
= 0V, 1.2V
V
CC
= +3.0V, I
AIN_
= I
BIN_
= 15mA,
V_
OUTA_
= V_
OUTB_
= 0V (Note 4)
V
CC
= +3.0V, I
AIN_
= I
BIN_
= 15mA,
V_
OUTA_
= V_
OUTB_
= 0V, 1.2V (Note 5)
-1
-0.3
6.4
0.2
0.3
V
CC
-
1.8
8.4
1.5
1
V
I
I
I
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
V
CC
= +3.6V, V
AIN_
= V
BIN_
= 0V, 1.2V;
I_
OUTA_(OFF),
V
_OUTA_
or V
_OUTB_
= 1.2V, 0V
I_
OUTB_(OFF)
(MAX4888B)
I
AIN_(ON),
I
BIN_(ON)
V
CC
= +3.6V , V
AIN_
= V
BIN_
= 0V, 1.2V;
V
_OUTA_
or V
_OUTB_
= V
AIN_
= V
BIN_
or
unconnected (MAX4888B)
All other ports are unconnected
(MAX4888C)
All other ports are unconnected
(MAX4888C)
+1
FA
AIN_, BIN_ On-Leakage Current
-1
+1
FA
Output Short-Circuit Current
Output Open-Circuit Voltage
5
0.2
0.6
15
0.9
FA
V
2
Up to 8.0Gbps Dual Passive Switches
ELECTRICAL CHARACTERISTICS (continued)
(V
CC
= 3.3V
Q10%,
T
A
= -40NC to +85NC
,
unless otherwise noted. Typical values are at V
CC
= 3.3V, T
A
= +25NC, unless otherwise
noted.) (Note 3)
PARAMETER
AC PERFORMANCE
Switch Turn-On Time
Switch Turn-Off Time
Propagation Delay
Output Skew Between Pairs
Output Skew Between Same
Pair
t
ON_SEL
t
OFF_SEL
t
PD
t
SK1
t
SK2
Z
S
= Z
L
= 50I
Z
S
= Z
L
= 50I, Figure 1, measured at
500MHz
Z
S
= Z
L
= 50I, Figure 2, measured at
500MHz
Z
S
= Z
L
= 50I, Figure 2, measured at
500MHz
Z
S
= Z
L
= 50I, Figure2
0Hz < f
P
2.8GHz
Differential Return Loss (Note 6)
S
DD11
2.8GHz < f
P
5.0GHz
5.0GHz < f
P
8.0GHz
f > 8.0GHz
Differential Insertion Loss
Bandwidth
S
DD21
S
DD12
/S
DD21
0Hz < f
P
2.5GHz
Differential Crosstalk (Note 6)
S
DDCTK
2.5GHz < f
P
5.0GHz
5.0GHz < f
P
8.0GHz
f > 8.0GHz
0Hz < f
P
2.5GHz
Differential Off-Isolation (Note 6)
S
DD21_OFF
2.5GHz < f
P
5.0GHz
5.0GHz < f
P
8.0GHz
f > 8.0GHz
CONTROL INPUT
Input Logic-High
Input Logic-Low
Input Logic Hysteresis
POWER SUPPLY
Power-Supply Range
V
CC
Supply Current
V
CC
I
CC
3.0
3.6
1
V
mA
V
IH
V
IL
V
HYST
130
1.4
0.6
V
V
mV
Table 1
8
-30
-25
-35
-35
-15
-12
-12
-12
dB
dB
-14
-8
-5
-1
dB
GHz
dB
65
7
43
8
10
ns
ns
ps
ps
ps
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
MAX4888B/MAX4888C
Note 3:
All units are 100% production tested at T
A
= +85NC. Limits over the operating temperature range are guaranteed by
design and characterization and are not production tested.
Note 4:
DR
ON
= R
ON(MAX)
- R
ON(MIN)
.
Note 5:
Flatness is defined as the difference between the maximum and minimum value of on-resistance as measured over the
specified analog-signal range.
Note 6:
Guaranteed by design; not production tested.
3
Up to 8.0Gbps Dual Passive Switches
MAX4888B/MAX4888C
Test Circuits/Timing Diagrams
SOURCE
MAX4888B
MAX4888C
Z
S
V
OUT
Z
L
SEL
LOAD
Σ
SEL
50%
50%
90%
V
OUT
10%
t
ON_SEL
t
OFF_SEL
THE FREQUENCY OF THE SIGNAL SHOULD BE ABOVE THE HIGHPASS FILTER CORNER OF THE COUPLING CAPACITORS.
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