ICS840051
F
EMTO
C
LOCKS
™ C
RYSTAL
-
TO
-
LVCMOS/LVTTL C
LOCK
G
ENERATOR
NRND – Not Recommend for New Designs - 8/30/2013
For replacement device use ICS840N051BGI
NRND
G
ENERAL
D
ESCRIPTION
The 840051 is a Gigabit Ethernet Clock Generator and a
member of the family of high performance devices from IDT.
T h e 8 4 0 0 5 1 c a n s y n t h e s i ze 1 0 G i g a b i t E t h e r n e t ,
SONET, or Ser ial ATA reference clock frequencies
with the appropriate choice of crystal and
output divider. The 840051 has excellent phase jitter
performance and is packaged in a small 8-pin TSSOP,
making it ideal for use in systems with limited board space.
F
EATURES
•
1 LVCMOS/LVTTL output, 15Ω output impedance
•
Crystal oscillator interface designed for
18pF parallel resonant crystals
•
Output frequency range: 70MHz - 170MHz
•
VCO range: 560MHz - 680MHz
•
RMS phase jitter at 155.52MHz (1.875MHz - 20MHz):
0.48ps (typical)
•
RMS phase noise at 155.52MHz
Offset Noise Power
100Hz ................-99.7 dBc/Hz
1KHz .................-120 dBc/Hz
10KHz .................-128 dBc/Hz
100KHz .................-127 dBc/Hz
•
3.3V operating supply
•
0°C to 70°C ambient operating temperature
•
Lead-Free fully RoHS compliant
•
Industrial temperature information available upon request
•
Not Recommended For New Designs
F
REQUENCY
T
ABLE
Inputs
Crystal Frequency (MHz)
20.141601
20.141601
19.53125
19.53125
19.44
19.44
18.75
18.75
FREQ_SEL
0
1
0
1
0
1
0
1
•
For New Designs use ICS840N051BGI
Output Frequency
(MHz)
161.132812
80.566406
156.25
78.125
155.52
77.76
150
75
B
LOCK
D
IAGRAM
OE Pullup
FREQ_SEL Pulldown
P
IN
A
SSIGNMENT
V
DDA
OE
XTAL_OUT
XTAL_IN
Q0
1
2
3
4
8
7
6
5
V
DD
Q0
GND
FREQ_SEL
XTAL_IN
OSC
XTAL_OUT
Phase
Detector
VCO
560MHz-680MHz
0 ÷4 (default)
1 ÷8
840051
8-Lead TSSOP
4.40mm x 3.0mm x 0.925mm
package body
G Package
Top View
÷32
(fixed)
840051
www.idt.com
1
REV. A 9/1/15
ICS840051
F
EMTO
C
LOCKS
™ C
RYSTAL
-
TO
-
LVCMOS/LVTTL C
LOCK
G
ENERATOR
NRND – Not Recommend for New Designs - 8/30/2013
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1
2
3, 4
5
6
7
8
Name
V
DDA
OE
XTAL_OUT,
XTAL_IN
FREQ_SEL
GND
Q0
V
DD
Power
Input
Input
Input
Power
Output
Power
Pullup
Type
Description
Analog supply pin.
Output enable pin. When HIGH, Q0 output is enabled. When LOW, forces
Q0 to HiZ state. LVCMOS/LVTTL interface levels. See Table 3A.
Crystal oscillator interface. XTAL_IN is the input,
XTAL_OUT is the output.
Power supply ground.
Single-ended clock output. LVCMOS/LVTTL interface levels.
15Ω output impedance.
Core supply pin.
NRND
Pulldown Frequency select pin. LVCMOS/LVTTL interface levels. See Table 3B.
NOTE:
Pullup and Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
C
PD
R
PULLUP
R
PULLDOWN
R
OUT
Parameter
Input Capacitance
Power Dissipation Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Output Impedance
V
DD
, V
DDA
= 3.465V
Test Conditions
Minimum
Typical
4
7
51
51
15
Maximum
Units
pF
pF
KΩ
KΩ
Ω
T
ABLE
3A. C
ONTROL
F
UNCTION
T
ABLE
Control Input
OE
0
1
Output
Q0
Hi-Z
Active
T
ABLE
3B. FREQ_SEL F
UNCTION
T
ABLE
Control Input
FRE_SEL
0
1
N Divider
÷4 (default)
÷8
840051
www.idt.com
2
REV. A 9/1/15
ICS840051
F
EMTO
C
LOCKS
™ C
RYSTAL
-
TO
-
LVCMOS/LVTTL C
LOCK
G
ENERATOR
NRND – Not Recommend for New Designs - 8/30/2013
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
Inputs, V
I
Outputs, V
O
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
4.6V
-0.5V to V
DD
+ 0.5 V
-0.5V to V
DD
+ 0.5V
101.7°C/W (0 mps)
-65°C to 150°C
NRND
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions
beyond those listed in the
DC Characteristics
or
AC Charac-
teristics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDA
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol
V
DD
V
DDA
I
DD
I
DDA
Parameter
Core Supply Voltage
Analog Supply Voltage
Power Supply Current
Analog Supply Current
Test Conditions
Minimum
3.135
3.135
Typical
3.3
3.3
Maximum
3.465
3.465
60
10
Units
V
V
mA
mA
T
ABLE
4B. LVCMOS/LVTTL DC C
HARACTERISTICS
,
V
DD
= V
DDA
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol
V
IH
V
IL
I
IH
I
IL
V
OH
V
OL
Parameter
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
OE
FREQ_SEL
OE
FREQ_SEL
V
DD
= V
IN
= 3.465V
V
DD
= V
IN
= 3.465V
V
DD
= 3.465V, V
IN
= 0V
V
DD
= 3.465V, V
IN
= 0V
-150
-5
2.6
0.5
Test Conditions
Minimum
2
-0.3
Typical
Maximum
V
DD
+ 0.3
0.8
5
150
Units
V
V
µA
µA
µA
µA
V
V
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
NOTE 1: Outputs terminated with 50Ω to V
DD
/2. See Parameter Measurement Information Section,
“3.3V Output Load Test Circuit”.
T
ABLE
5. C
RYSTAL
C
HARACTERISTICS
Parameter
Mode of Oscillation
Frequency
Equivalent Series Resistance (ESR)
Shunt Capacitance
17.5
Test Conditions
Minimum
Typical
Fundamental
21.25
50
7
MHz
Ω
pF
Maximum
Units
840051
www.idt.com
3
REV. A 9/1/15
ICS840051
F
EMTO
C
LOCKS
™ C
RYSTAL
-
TO
-
LVCMOS/LVTTL C
LOCK
G
ENERATOR
NRND – Not Recommend for New Designs - 8/30/2013
T
ABLE
6. AC C
HARACTERISTICS
,
V
DD
= V
DDA
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol
f
OUT
tjit(Ø)
t
R
/ t
F
odc
Parameter
Output Frequency
RMS Phase Jitter ( Random);
NOTE 1
Output Rise/Fall Time
Output Duty Cycle
155.52MHz, Integration Range:
1.875MHz - 20MHz
77.76MHz, Integration Range:
1.875MHz - 20MHz
20% to 80%
200
48
Test Conditions
Minimum
70
0.48
0.45
500
52
Typical
NRND
Maximum
170
Units
MHz
ps
ps
ps
%
NOTE 1: Please refer to the Phase Noise Plots.
840051
www.idt.com
4
REV. A 9/1/15
ICS840051
F
EMTO
C
LOCKS
™ C
RYSTAL
-
TO
-
LVCMOS/LVTTL C
LOCK
G
ENERATOR
NRND – Not Recommend for New Designs - 8/30/2013
0
-10
-20
-30
-40
-50
T
YPICAL
P
HASE
N
OISE AT
155.52MH
Z
NRND
N
OISE
P
OWER
dBc
Hz
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
100
1k
10k
RMS Phase Jitter (Random)
1.875Mhz to 20MHz = 0.48ps (typical)
Raw Phase Noise Data
➤
Phase Noise Result by adding
10GigE Filter to raw data
100k
1M
10M
100M
O
FFSET
F
REQUENCY
(H
Z
)
0
-10
-20
-30
-40
-50
T
YPICAL
P
HASE
N
OISE AT
77.76MH
Z
N
OISE
P
OWER
dBc
Hz
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
100
1k
10k
RMS Phase Jitter (Random)
1.875Mhz to 20MHz = 0.45ps (typical)
Raw Phase Noise Data
➤
Phase Noise Result by adding
10GigE Filter to raw data
1M
10M
100M
100k
www.idt.com
5
O
FFSET
F
REQUENCY
(H
Z
)
840051
REV. A 9/1/15
➤
➤
10GigE Filter
155.52MHz
➤
10GigE Filter
77.76MHz
➤
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
