19-3591; Rev 2; 3/07
KIT
ATION
EVALU
BLE
AVAILA
16-Bit, 250Msps, High-Dynamic-Performance,
Dual DAC with LVDS Inputs
General Description
The MAX5878 is an advanced 16-bit, 250Msps, dual
digital-to-analog converter (DAC). This DAC meets the
demanding performance requirements of signal synthesis
applications found in wireless base stations and other
communications applications. Operating from +3.3V and
+1.8V supplies, this dual DAC offers exceptional dynamic
performance such as 76dBc spurious-free dynamic range
(SFDR) at f
OUT
= 16MHz and supports update rates of
250Msps, with a power dissipation of only 296mW.
The MAX5878 utilizes a current-steering architecture
that supports a 2mA to 20mA full-scale output current
range, and allows a 0.1V
P-P
to 1V
P-P
differential output
voltage swing. The device features an integrated +1.2V
bandgap reference and control amplifier to ensure
high-accuracy and low-noise performance. A separate
reference input (REFIO) allows for the use of an exter-
nal reference source for optimum flexibility and
improved gain accuracy.
The clock inputs of the MAX5878 accept both LVDS
and LVPECL-compatible voltage levels. The device fea-
tures an interleaved data input that allows a single
LVDS bus to support both DACs. The MAX5878 is avail-
able in a 68-pin QFN package with an exposed paddle
(EP) and is specified for the extended temperature
range (-40°C to +85°C).
Refer to the MAX5876 and MAX5877 data sheets for
pin-compatible 12-bit and 14-bit versions of the
MAX5878, respectively. Refer to the MAX5875 data
sheet for a CMOS-compatible version of the MAX5878.
Features
♦
250Msps Output Update Rate
♦
Noise Spectral Density = -164dBFS/Hz
at f
OUT
= 16MHz
♦
Excellent SFDR and IMD Performance
SFDR = 76dBc at f
OUT
= 16MHz (to Nyquist)
SFDR = 71dBc at f
OUT
= 80MHz (to Nyquist)
IMD = -90dBc at f
OUT
= 10MHz
IMD = -72dBc at f
OUT
= 80MHz
♦
ACLR = 75dB at f
OUT
= 61MHz
♦
2mA to 20mA Full-Scale Output Current
♦
LVDS-Compatible Digital and Clock Inputs
♦
On-Chip +1.20V Bandgap Reference
♦
Low 296mW Power Dissipation
♦
Compact 68 QFN-EP Package (10mm x 10mm)
♦
Evaluation Kit Available (MAX5878EVKIT)
MAX5878
Ordering Information
PART
MAX5878EGK-D
MAX5878EGK+D
TEMP RANGE
-40°C to +85°C
-40°C to +85°C
PIN-
PACKAGE
68 QFN-EP*
68 QFN-EP*
PKG
CODE
G6800-4
G6800-4
*EP
= Exposed pad.
+
= Lead-free package. D = Dry pack.
Pin Configuration
B10N
B11N
B12N
B10P
B11P
B5N
B6N
B7N
B8N
B9N
B4P
B5P
B6P
B7P
B8P
Base Stations: Single/Multicarrier UMTS, CDMA, GSM
Communications: Fixed Broadband Wireless Access,
Point-to-Point Microwave
Direct Digital Synthesis (DDS)
Cable Modem Termination Systems (CMTS)
Automated Test Equipment (ATE)
Instrumentation
68
67 66 65 64
63 62 61 60 59 58
B4N
B3P
B3N
B2P
B2N
B1P
B1N
B0P
B0N
GND
DV
DD3.3
GND
GND
AV
DD3.3
GND
REFIO
FSADJ
B9P
Applications
TOP VIEW
DV
DD1.8
57 56 55 54 53 52
51
50
49
48
47
46
45
44
43
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
B12P
B13N
B13P
B14N
B14P
B15N
B15P
SELIQN
SELIQP
XORP
XORN
PD
TORB
CLKP
CLKN
GND
AV
CLK
Selector Guide
PART
MAX5873
MAX5874
MAX5875
MAX5876
MAX5877
MAX5878
RESOLUTION
(BITS)
12
14
16
12
14
16
UPDATE
RATE (Msps)
200
200
200
250
250
250
LOGIC
INPUTS
CMOS
CMOS
CMOS
LVDS
LVDS
LVDS
MAX5878
42
41
40
39
38
37
36
35
AV
DD1.8
GND
GND
GND
GND
GND
OUTQN
OUTQP
OUTIN
DACREF
AV
DD3.3
AV
DD3.3
OUTIP
AV
DD3.3
AV
DD3.3
GND
QFN
________________________________________________________________
Maxim Integrated Products
AV
DD1.8
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
16-Bit, 250Msps, High-Dynamic-Performance,
Dual DAC with LVDS Inputs
MAX5878
ABSOLUTE MAXIMUM RATINGS
AV
DD1.8
, DV
DD1.8
to GND, DACREF...................-0.3V to +2.16V
AV
DD3.3
, DV
DD3.3
, AV
CLK
to GND, DACREF ........-0.3V to +3.9V
REFIO, FSADJ to
GND, DACREF..................................-0.3V to (AV
DD3.3
+ 0.3V)
OUTIP, OUTIN, OUTQP,
OUTQN to GND, DACREF..................-1V to (AV
DD3.3
+ 0.3V)
CLKP, CLKN to GND, DACREF.............-0.3V to (AV
CLK
+ 0.3V)
B15P/B15N–B0P/B0N, XORN, XORP, SELIQN,
SELIQP to GND, DACREF ..................-0.3V to (DV
DD1.8
+ 0.3V)
TORB, PD to GND, DACREF ..............-0.3V to (DV
DD3.3
+ 0.3V)
Continuous Power Dissipation (T
A
= +70°C)
68-Pin QFN-EP
(derate 41.7mW/°C above +70°C) (Note 1) ............3333.3mW
Thermal Resistance
θ
JA
(Note 1)...................................+24°C/W
Operating Temperature Range ......................... -40°C to +85°C
Junction Temperature .................................................... +150°C
Storage Temperature Range ........................... -60°C to +150°C
Lead Temperature (soldering, 10s) ............................... +300°C
Note 1:
Thermal resistors based on a multilayer board with 4 x 4 via array in exposed paddle area.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(AV
DD3.3
= DV
DD3.3
= AV
CLK
= +3.3V, AV
DD1.8
= DV
DD1.8
= +1.8V, GND = 0, f
CLK
= 2 x f
DAC
, external reference V
REFIO
= +1.25V, out-
put load 50Ω double-terminated, transformer-coupled output, I
OUTFS
= 20mA, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values
are at T
A
= +25°C.) (Note 2)
PARAMETER
STATIC PERFORMANCE
Resolution
Integral Nonlinearity
Differential Nonlinearity
Offset Error
Offset-Drift Tempco
Full-Scale Gain Error
Gain-Drift Tempco
Full-Scale Output Current
Output Compliance
Output Resistance
Output Capacitance
DYNAMIC PERFORMANCE
Clock Frequency
Output Update Rate
Noise Spectral Density
f
CLK
f
DAC
f
DAC
= 150MHz
f
DAC
= 250MHz
f
OUT
= 16MHz, -12dBFS
f
OUT
= 80MHz, -12dBFS
2
1
-164
-161
500
250
MHz
Msps
dBFS/
Hz
R
OUT
C
OUT
I
OUTFS
GE
FS
External reference
Internal reference
External reference
(Note 3)
Single-ended
2
-0.5
1
5
-4.6
INL
DNL
OS
Measured differentially
Measured differentially
-0.025
16
±3
±2
±0.001
±10
-0.6
±100
±50
20
+1.1
+4.6
+0.025
Bits
LSB
LSB
%FS
ppm/°C
%FS
ppm/°C
mA
V
MΩ
pF
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
2
_______________________________________________________________________________________
16-Bit, 250Msps, High-Dynamic-Performance,
Dual DAC with LVDS Inputs
ELECTRICAL CHARACTERISTICS (continued)
(AV
DD3.3
= DV
DD3.3
= AV
CLK
= +3.3V, AV
DD1.8
= DV
DD1.8
= +1.8V, GND = 0, f
CLK
= 2 x f
DAC
, external reference V
REFIO
= +1.25V, out-
put load 50Ω double-terminated, transformer-coupled output, I
OUTFS
= 20mA, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values
are at T
A
= +25°C.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
f
OUT
= 1MHz, 0dBFS
f
OUT
= 1MHz, -6dBFS
f
DAC
= 100MHz
f
OUT
= 1MHz, -12dBFS
f
OUT
= 10MHz, -12dBFS
f
OUT
= 30MHz, -12dBFS
Spurious-Free Dynamic Range
to Nyquist
f
OUT
= 10MHz, -12dBFS
SFDR
f
DAC
= 200MHz
f
OUT
= 16MHz, -12dBFS
f
OUT
= 50MHz, -12dBFS
f
OUT
= 80MHz, -12dBFS
f
OUT
= 10MHz, -12dBFS
f
DAC
= 250MHz
f
OUT
= 50MHz, -12dBFS
f
OUT
= 80MHz, -12dBFS
f
OUT
= 100MHz, -12dBFS
Spurious-Free Dynamic Range,
25MHz Bandwidth
SFDR
f
DAC
= 150MHz
f
DAC
= 100MHz
Two-Tone IMD
TTIMD
f
DAC
= 200MHz
Four-Tone IMD, 1MHz
Frequency Spacing, GSM Model
Adjacent Channel Leakage Power
Ratio 3.84MHz Bandwidth,
W-CDMA Model
Output Bandwidth
INTER-DAC CHARACTERISTICS
Gain Matching
Gain-Matching Tempco
Phase Matching
Phase-Matching Tempco
Channel-to-Channel Crosstalk
REFERENCE
Internal Reference Voltage Range
V
REFIO
1.14
1.2
1.26
V
∆Gain
∆Gain/°C
∆Phase
f
OUT
= 60MHz
∆Phase/°C
f
OUT
= 60MHz
f
DAC
= 200Msps, f
OUT
= 50MHz, 0dBFS
f
OUT
= DC - 80MHz
f
OUT
= DC
-0.25
±0.2
+0.01
±20
±0.25
±0.002
86
+0.25
dB
ppm/°C
Degrees
Degrees/
°C
dB
FTIMD
f
DAC
= 150MHz
f
DAC
=
184.32MHz
(Note 4)
f
OUT
= 16MHz, -12dBFS
f
OUT1
= 9MHz, -7dBFS;
f
OUT2
= 10MHz, -7dBFS
f
OUT1
= 79MHz, -7dBFS;
f
OUT2
= 80MHz, -7dBFS
f
OUT
= 16MHz, -12dBFS
67
MIN
TYP
94
87
81
81
79
75
76
73
71
74
75
71
69
78
-90
dBc
-72
-80
dBc
dBc
dBc
MAX
UNITS
MAX5878
ACLR
BW
-1dB
f
OUT
= 61.44MHz
75
240
dB
MHz
_______________________________________________________________________________________
3
16-Bit, 250Msps, High-Dynamic-Performance,
Dual DAC with LVDS Inputs
MAX5878
ELECTRICAL CHARACTERISTICS (continued)
(AV
DD3.3
= DV
DD3.3
= AV
CLK
= +3.3V, AV
DD1.8
= DV
DD1.8
= +1.8V, GND = 0, f
CLK
= 2 x f
DAC
, external reference V
REFIO
= +1.25V, out-
put load 50Ω double-terminated, transformer-coupled output, I
OUTFS
= 20mA, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values
are at T
A
= +25°C.) (Note 2)
PARAMETER
Reference Input Compliance
Range
Reference Input Resistance
Reference Voltage Drift
Output Fall Time
Output Rise Time
Output-Voltage Settling Time
Output Propagation Delay
Glitch Impulse
Output Noise
TIMING CHARACTERISTICS
Data to Clock Setup Time
Data to Clock Hold Time
Data Latency
Minimum Clock Pulse-Width High
Minimum Clock Pulse-Width Low
Differential Input-Logic High
Differential Input-Logic Low
Common-Mode Voltage Range
Differential Input Resistance
Input Capacitance
CMOS LOGIC INPUTS (PD, TORB)
Input-Logic High
Input-Logic Low
Input Leakage Current
PD, TORB Internal Pulldown
Resistance
Input Capacitance
CLOCK INPUTS (CLKP, CLKN)
Differential Input
Voltage Swing
Sine wave
Square wave
> 1.5
> 0.5
V
P-P
C
IN
V
IH
V
IL
I
IN
V
PD
= V
TORB
= 3.3V
-20
1
1.5
2.5
0.7 x
DV
DD3.3
0.3 x
DV
DD3.3
+20
V
V
µA
MΩ
pF
t
CH
t
CL
V
IH
V
IL
V
CMR
R
IN
C
IN
(Note 7)
-100
1.125
110
2.5
1.375
t
SETUP
t
HOLD
Referenced to rising edge of clock (Note 6)
Referenced to rising edge of clock (Note 6)
Latency to I output
Latency to Q output
CLKP, CLKN
CLKP, CLKN
-1.2
2.0
9
8
0.9
0.9
100
ns
ns
Clock
Cycles
ns
ns
mV
mV
V
Ω
pF
n
OUT
SYMBOL
V
REFIOCR
R
REFIO
TCO
REF
t
FALL
t
RISE
t
SETTLE
t
PD
90% to 10% (Note 5)
10% to 90% (Note 5)
Output settles to 0.025% FS (Note 5)
Excluding data latency (Note 5)
Measured differentially
I
OUTFS
= 2mA
I
OUTFS
= 20mA
CONDITIONS
MIN
0.125
10
±25
0.7
0.7
14
1.1
1
30
30
TYP
MAX
1.260
UNITS
V
kΩ
ppm/°C
ns
ns
ns
ns
pV
•
s
pA/√Hz
ANALOG OUTPUT TIMING (See Figure 4)
LVDS LOGIC INPUTS (B15P/B15N–B0P/B0N, XORN, XORP, SELIQN, SELIQP)
4
_______________________________________________________________________________________
16-Bit, 250Msps, High-Dynamic-Performance,
Dual DAC with LVDS Inputs
ELECTRICAL CHARACTERISTICS (continued)
(AV
DD3.3
= DV
DD3.3
= AV
CLK
= +3.3V, AV
DD1.8
= DV
DD1.8
= +1.8V, GND = 0, f
CLK
= 2 x f
DAC
, external reference V
REFIO
= +1.25V, out-
put load 50Ω double-terminated, transformer-coupled output, I
OUTFS
= 20mA, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values
are at T
A
= +25°C.) (Note 2)
PARAMETER
Differential Input Slew Rate
External Common-Mode Voltage
Range
Input Resistance
Input Capacitance
POWER SUPPLIES
Analog Supply Voltage Range
Digital Supply Voltage Range
Clock Supply Voltage Range
Analog Supply
Current
AV
DD3.3
AV
DD1.8
DV
DD3.3
DV
DD1.8
AV
CLK
I
AVDD3.3
+ I
AVCLK
I
AVDD1.8
I
DVDD3.3
I
DVDD1.8
Power Dissipation
Power-Supply
Rejection Ratio
P
DISS
PSRR
f
DAC
= 250Msps, f
OUT
= 16MHz
Power-down
f
DAC
= 250Msps, f
OUT
= 16MHz
Power-down
f
DAC
= 250Msps, f
OUT
= 16MHz
Power-down
f
DAC
= 250Msps, f
OUT
= 16MHz
Power-down
f
DAC
= 250Msps, f
OUT
= 16MHz
Power-down
AV
DD3.3
= AV
CLK
= DV
DD3.3
= +3.3V
±5%
(Notes 8, 9)
-0.1
3.135
1.710
3.135
1.710
3.135
3.3
1.8
3.3
1.8
3.3
52
1
32
1
0.2
1
36
4
296
16
+0.1
331
40
1
36
3.465
1.890
3.465
1.890
3.465
58
V
V
V
mA
µA
mA
µA
mA
µA
mA
µA
mW
µW
%FS/V
SYMBOL
SR
CLK
V
COM
R
CLK
C
CLK
(Note 8)
CONDITIONS
MIN
TYP
>100
AV
CLK
/ 2
±0.3
5
2.5
MAX
UNITS
V/µs
V
kΩ
pF
MAX5878
Digital Supply
Current
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
Specifications at T
A
≥
+25°C are guaranteed by production testing. Specifications at T
A
< +25°C are guaranteed by design.
Nominal full-scale current I
OUTFS
= 32 x I
REF
.
This parameter does not include update-rate-dependent effects of sin(x)/x filtering inherent in the MAX5878.
Parameter measured single-ended into a 50Ω termination resistor.
Not production tested. Guaranteed by design.
No termination resistance between XORP and XORN.
A differential clock input slew rate of > 100V/µs is required to achieve the specified dynamic performance.
Parameter defined as the change in midscale output caused by a ±5% variation in the nominal supply voltage.
_______________________________________________________________________________________
5
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