74LV4066
Quad bilateral switches
Rev. 03 — 4 July 2005
Product data sheet
1. General description
The 74LV4066 is a low-voltage Si-gate CMOS device that is pin and function compatible
with the 74HC4066 and 74HCT4066.
The 74LV4066 has four independent switches. Each switch has two input/output pins
(nY, nZ) and an active HIGH enable input pin (nE). When nE is LOW the corresponding
analog switch is turned off.
The 74LV4066 has a ON-resistance which is reduced in comparison with the 74HCT4066.
2. Features
s
s
s
s
Optimized for low-voltage applications: 1.0 V to 3.6 V
Typical V
OLP
(output ground bounce): < 0.8 V at V
CC
= 3.3 V and T
amb
= 25
°C
Accepts TTL input levels between V
CC
= 2.7 V and V
CC
= 3.6 V
Very low ON-resistance:
x
60
Ω
(typical) at V
CC
= 2.0 V
x
35
Ω
(typical) at V
CC
= 3.0 V
x
25
Ω
(typical) at V
CC
= 4.5 V
s
ESD protection:
x
HBM EIA/JESD22-A114C exceeds 2000 V
x
MM EIA/JESD22-A115-A exceeds 200 V
s
Specified from
−40 °C
to +80
°C
and from
−40 °C
to +125
°C
Philips Semiconductors
74LV4066
Quad bilateral switches
3. Quick reference data
Table 1:
Quick reference data
GND = 0 V; T
amb
= 25
°
C; t
r
= t
f
≤
2.5 ns; C
L
= 15 pF; R
L
= 1 k
Ω
.
Symbol
t
PZL
, t
PZH
t
PLZ
, t
PHZ
C
i
C
S
C
PD
[1]
Parameter
turn-on time nE to V
os
turn-off time nE to V
os
input capacitance
maximum switch
capacitance
power dissipation
capacitance per switch
Conditions
V
CC
= 3.3 V
V
CC
= 3.3 V
Min
-
-
-
-
Typ
10
13
3.5
8
11
Max
-
-
-
-
-
Unit
ns
ns
pF
pF
pF
V
CC
= 3.3 V
[1] [2]
-
C
PD
is used to determine the dynamic power dissipation (P
D
in
µW).
P
D
= C
PD
×
V
CC2
×
f
i
×
N +
Σ[(C
L
+ C
S
)
×
V
CC2
×
f
o
] where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
C
S
= maximum switch capacitance in pF;
V
CC
= supply voltage in V;
N = number of inputs switching;
Σ[(C
L
+ C
S
)
×
V
CC2
×
f
o
] = sum of the outputs.
[2]
The condition is V
I
= GND to V
CC
.
4. Ordering information
Table 2:
Ordering information
Temperature range Name
74LV4066N
74LV4066D
74LV4066DB
−40 °C
to +125
°C
−40 °C
to +125
°C
−40 °C
to +125
°C
DIP14
SO14
SSOP14
Description
plastic dual in-line package;
14 leads (300 mil)
plastic small outline package;
14 leads; body width 3.9 mm
Version
SOT27-1
SOT108-1
Type number Package
plastic shrink small outline package; SOT337-1
14 leads; body width 5.3 mm
SOT402-1
74LV4066PW
−40 °C
to +125
°C
TSSOP14 plastic thin shrink small outline
package; 14 leads; body width
4.4 mm
9397 750 15209
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 03 — 4 July 2005
2 of 23
Philips Semiconductors
74LV4066
Quad bilateral switches
5. Functional diagram
1
13
4
5
8
6
11
12
1Y
1E
1Z
1
2
1
2
13 #
4
5#
3
8
9
6#
11
12 #
(a)
1
X1
1
X1
1
X1
1
X1
(b)
1
2
2Y
2E
3Y
3E
4Y
4E
2Z
3
13 #
4
5#
1
3
3Z
9
8
6#
11
1
9
10
4Z
1
10
10
12 #
001aad269
001aad270
Fig 1. Logic symbol
Fig 2. IEC logic diagram
nY
nE
V
CC
V
CC
GND
nZ
001aad271
Fig 3. Logic diagram (one switch)
9397 750 15209
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 03 — 4 July 2005
3 of 23
Philips Semiconductors
74LV4066
Quad bilateral switches
6. Pinning information
6.1 Pinning
1Y
1Z
2Z
2Y
2E
3E
GND
1
2
3
4
5
6
7
001aad268
14 V
CC
13 1E
12 4E
4066
11 4Y
10 4Z
9
8
3Z
3Y
Fig 4. Pin configuration
6.2 Pin description
Table 3:
Symbol
1Y
1Z
2Z
2Y
2E
3E
GND
3Y
3Z
4Z
4Y
4E
1E
V
CC
Pin description
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Description
independent input or output
independent output or input
independent output or input
independent input or output
enable input
enable input
ground (0 V)
independent input or output
independent output or input
independent output or input
independent input or output
enable input
enable input
supply voltage
7. Functional description
7.1 Function table
Table 4:
Input nE
LOW
HIGH
9397 750 15209
Function table
Switch
off
on
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 03 — 4 July 2005
4 of 23
Philips Semiconductors
74LV4066
Quad bilateral switches
8. Limiting values
Table 5:
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to
GND (ground = 0 V).
Symbol Parameter
V
CC
I
IK
I
OK
I
S
T
stg
P
tot
supply voltage
input diode current
output diode current
switch source or sink
current
storage temperature
total power dissipation
DIP14 package
SO14 package
(T)SSOP14 package
[1]
[2]
[3]
[4]
DIP14 package: P
tot
derates linearly with 12 mW/K above 70
°C.
SO14 package: P
tot
derates linearly with 8 mW/K above 70
°C.
(T)SSOP14 package: P
tot
derates linearly with 5.5 mW/K above 60
°C.
Conditions
V
I
<
−0.5
V or V
I
> V
CC
+ 0.5 V
V
O
<
−0.5
V or V
O
> V
CC
+ 0.5 V
V
O
=
−0.5
V to (V
CC
+ 0.5 V)
[1]
Min
−0.5
-
-
-
−65
Max
+7.0
±20
±50
±25
+150
750
500
400
Unit
V
mA
mA
mA
°C
mW
mW
mW
T
amb
=
−40 °C
to +125
°C
[2]
[3]
[4]
-
-
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
9. Recommended operating conditions
Table 6:
Symbol
V
CC
V
I
V
O
T
amb
t
r
, t
f
Recommended operating conditions
Parameter
supply voltage
input voltage
output voltage
ambient temperature
input rise and fall times
in free air
V
CC
= 1.0 V to 2.0 V
V
CC
= 2.0 V to 2.7 V
V
CC
= 2.7 V to 3.6 V
V
CC
= 3.6 V to 5.5 V
[1]
Conditions
[1]
Min
1.0
0
0
−40
-
-
-
-
Typ
3.3
-
-
-
-
-
-
-
Max
6
V
CC
V
CC
+125
500
200
100
50
Unit
V
V
V
°C
ns/V
ns/V
ns/V
ns/V
The static characteristics are guaranteed from V
CC
= 1.2 V to V
CC
= 5.5 V, but LV devices are guaranteed to
function down to V
CC
= 1.0 V (with input levels GND or V
CC
).
9397 750 15209
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 03 — 4 July 2005
5 of 23
嵌入式系统
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