19-2215; Rev 6; 10/07
KIT
ATION
EVALU
E
BL
AVAILA
+3.3V, 2.5Gbps/2.7Gbps, SDH/SONET 4:1
Serializer with Clock Synthesis
General Description
The MAX3892 serializer is ideal for converting 4-bit-
wide, 622Mbps parallel data to 2.5Gbps serial data in
DWDM and SONET/SDH applications. A 4
✕
4-bit FIFO
allows for any static delay between the parallel output
clock and parallel input clock. Delay variation up to a
unit interval (UI) is allowed after reset. A fully integrated
phase-locked loop (PLL) synthesizes an internal
2.5GHz serial clock from a 622MHz, 155.5MHz,
77.8MHz, or 38.9MHz reference clock. A selectable
dual VCO allows excellent jitter performance at both
SONET and forward-error correction (FEC) data rates.
Operating from a single 3.3V supply, this device
accepts low-voltage differential-signal (LVDS) clock and
data inputs for interfacing with high-speed digital circuit-
ry, and delivers current-mode logic (CML) serial data
and clock outputs. A loopback data output is provided
to facilitate system diagnostic testing. The MAX3892 is
available in the extended temperature range (-40°C to
+85°C) in 44-pin QFN and TQFN packages.
♦
Single +3.3V Supply
♦
455mW Power Consumption
♦
1.4ps
RMS
Maximum Jitter Generation
♦
4
✕
4-Bit FIFO Input Buffer
♦
622Mbps/666Mbps Parallel to 2.5Gbps/2.7Gbps
Serial Conversion
♦
622MHz/667MHz or 311MHz/333MHz Clock Input
♦
On-Chip Clock Synthesizer
♦
Multiple Clock Reference Frequencies:
(622.08MHz, 155.52MHz, 77.76MHz, 38.88MHz) or
(666.51MHz, 166.63MHz, 83.31MHz, 41.66MHz)
♦
LVDS Parallel Clock and Data Inputs
♦
CML Serial Data and Clock Outputs
♦
Additional CML Output for System Loopback
Testing
Features
MAX3892
Applications
SONET/SDH OC-48 Transmission Systems
WDM Transponders
Add/Drop Multiplexers
Dense Digital Cross-Connects
Backplane Interconnects
PART
MAX3892EGH
Ordering Information
TEMP
RANGE
-40°C to +85°C
PIN-
PACKAGE
44 QFN
44 TQFN
PKG
CODE
G4477-3
T4477-3
MAX3892ETH+ -40°C to +85°C
+Denotes
a lead-free package.
Typical Application Circuit
LVPECL
100Ω
VCCVCO
C
Z
V
CC
RCLK-
LVDS
PDI0+
PDI0-
SONET/SDH
FRAMER
RCLK+ FIL
VCCVCO
CLKSET MODE RATESET
SDO+
SDO-
CML
MAX3273
CML
SCLKO+
SCLKO-
SLBEN
LASER
DRIVER
TTL
CML
PDI3+
PDI3-
MAX3892
LVDS
PCLKI+
PCLKI-
LVDS
PCLKO+
PCLKO-
RESET
FIFOERROR
SLBPD
SLBO+
SLBO-
MAX3882
OPTIONAL
FOR
SYSTEM
LOOPBACK
TEST
1:4 DESERIALIZER
WITH CDR
LOL
THIS SYMBOL REPRESENTS A TRANSMISSION
LINE OF CHARACTERISTIC IMPEDANCE Z
O
= 50Ω.
________________________________________________________________
Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
+3.3V, 2.5Gbps/2.7Gbps, SDH/SONET 4:1
Serializer with Clock Synthesis
MAX3892
ABSOLUTE MAXIMUM RATINGS
Supply Voltage V
CC
, VCCO, VCCVCO .....................-0.5V to +5V
All Inputs and FIL .......................................-0.5V to (V
CC
+ 0.5V)
LVDS Output Voltage (PCLKO±)................-0.5V to (V
CC
+ 0.5V)
CML Output Current (SDO±, SCLKO±, SLBO±) ................22mA
Continuous Power Dissipation (T
A
= +85°C)
44-Pin QFN (derate 25mW/°C above +85°C) ............1625mW
Operating Temperature Range ...........................-40°C to +85°C
Storage Temperature Range .............................-55°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(V
CC
= +3.0V to +3.6V, T
A
= -40°C to +85°C. Typical values are at V
CC
= +3.3V, differential LVDS load = 100Ω ±1%, T
A
= +25°C,
unless otherwise noted.) (Note 1)
PARAMETER
Supply Current
Input Voltage Range
Differential Input Voltage
Input Common-Mode Current
Threshold Hysteresis
Differential Input Resistance
R
IN
83
V
CC
-
1.16
V
CC
-
1.81
V
CC
- 1.3
>1.0
300
V
OH
V
OL
|V
OD
|
Δ|V
OD
|
1.125
Δ|V
OS
|
0.925
250
400
25
1.275
25
1900
1.475
LVPECL INPUT SPECIFICATIONS
(RCLK±)
Input High Voltage
Input Low Voltage
Input Bias Voltage
Single-Ended Input Resistance
Differential Input Voltage Swing
LVDS OUTPUT SPECIFICATIONS
(PCLKO±)
Output High Voltage
Output Low Voltage
Differential Output Voltage
Change in Magnitude of
Differential Output Voltage for
Complementary States
Offset Output Voltage
Change in Magnitude of Output
Offset Voltage for Complementary
States
V
V
mV
mV
V
mV
V
IH
V
IL
V
CC
-
0.88
V
CC
-
1.48
V
V
V
kΩ
mV
P-P
SYMBOL
I
CC
V
I
|V
ID
|
LVDS input V
OS
= 1.2V
(Note 2)
0
100
61
45
100
117
CONDITIONS
MIN
TYP
138
MAX
190
2400
UNITS
mA
mV
mV
µA
mV
Ω
LVDS INPUT SPECIFICATIONS
(PDI[3..0]±, PCLKI±)
2
_______________________________________________________________________________________
+3.3V, 2.5Gbps/2.7Gbps, SDH/SONET 4:1
Serializer with Clock Synthesis
DC ELECTRICAL CHARACTERISTICS (continued)
(V
CC
= +3.0V to +3.6V, T
A
= -40°C to +85°C. Typical values are at V
CC
= +3.3V, differential LVDS load = 100Ω ±1%, T
A
= +25°C,
unless otherwise noted.) (Note 1)
PARAMETER
Differential Output Resistance
Output Current
Output Current
Differential Output
Differential Output Resistance
Output Common-Mode Voltage
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Output High Voltage
Output Low Voltage
Input Current
V
IH
V
IL
I
IH
I
IL
V
OH
V
OL
I
OH
= 20µA
I
OL
= 1mA
Input = 0 or V
CC
-500
-30
-50
2.4
R
L
= 50Ω to V
CC
2.0
0.8
+10
+10
V
CC
0.4
+500
LVTTL SPECIFICATIONS
(RESET, RATESET, SLBEN, SLBPD FIFOERROR,
LOL)
V
V
µA
µA
V
V
µA
Shorted together
Shorted to ground
R
L
= 100Ω differential
640
83
800
100
V
CC
- 0.2
SYMBOL
CONDITIONS
MIN
80
TYP
MAX
140
12
40
1000
117
UNITS
Ω
mA
mA
mV
P-P
Ω
V
MAX3892
CML OUTPUT SPECIFICATIONS
(SDO±, SCLKO±, SLBO±)
PROGRAMMING INPUTS
(CLKSET, MODE)
AC ELECTRICAL CHARACTERISTICS
(V
CC
= +3.0V to +3.6V, T
A
= -40°C to +85°C. Typical values are at V
CC
= +3.3V, differential LVDS loads = 100Ω ±1%, CML loads =
50Ω ±1%, T
A
= +25°C, unless otherwise noted.) (Note 3)
PARAMETER
SYMBOL
CONDITIONS
RATESET = GND
RATESET = V
CC
MODE = OPEN or V
CC
MODE = SHORT or 30kΩ to GND
t
SU
t
H
(Note 4)
(Note 4)
-94
300
MIN
TYP
622
666
622
311
MAX
UNITS
PARALLEL INPUT SPECIFICATIONS
(PDI±, PCLKI±)
Parallel Input Data Rate
Parallel Input Clock Rate
Parallel Input Setup Time
Parallel Input Hold Time
Parallel Clock Output Rise/Fall
Time
Parallel Clock Output Duty Cycle
SERIAL OUTPUT SPECIFICATIONS
(SDO±, SCLKO±)
Serial Output Data Rate
Serial Data Output Rise/Fall Time
Serial Output Clock to Data Delay
t
r
, t
f
t
CLK-Q
RATESET = GND
RATESET = V
CC
20% to 80%
(Note 5)
-25
2.488
2.666
80
25
Gbps
ps
ps
Mbps
MHz
ps
ps
PARALLEL CLOCK OUTPUT SPECIFICATIONS
(PCLKO±)
t
r
, t
f
20% to 80%
100
46
200
54
ps
%
_______________________________________________________________________________________
3
+3.3V, 2.5Gbps/2.7Gbps, SDH/SONET 4:1
Serializer with Clock Synthesis
MAX3892
AC ELECTRICAL CHARACTERISTICS (continued)
(V
CC
= +3.0V to +3.6V, T
A
= -40°C to +85°C. Typical values are at V
CC
= +3.3V, differential LVDS loads = 100Ω ±1%, CML loads =
50Ω ±1%, T
A
= +25°C, unless otherwise noted.) (Note 3)
PARAMETER
Serial Clock Output Jitter
Generation
Serial Data Output Random Jitter
Serial Data Output Deterministic
Jitter
SYMBOL
JG
RJ
DJ
(Notes 6 and 7)
(Note 7)
(Note 8)
CONDITIONS
MIN
TYP
1.0
MAX
1.4
1.4
19
UNITS
ps
RMS
ps
RMS
ps
P-P
REFERENCE CLOCK INPUT SPECIFICATIONS
(RCLK)
Reference Clock Frequency
Tolerance
Reference Clock Input Duty Cycle
RESET INPUTS
(RESET)
Minimum Pulse Width of FIFO
Reset
Tolerated Drift Between PCLKI
and PCLKO After Reset
UI is PCLKO period
UI is PCLKO period
4
±1
UI
UI
±100
30
70
ppm
%
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Specifications at -40°C are guaranteed by design and characterization.
Measured with SLBO/CLK622 and SCLK outputs disabled and CML outputs open.
AC characteristics are guaranteed by design and characterization.
In 622MHz clock mode, the parallel data is clocked in by the rising edge of the 622MHz/666MHz parallel clock input. In the
311MHz clock mode, the parallel data is clocked in on both the rising and falling edges of the clock. The parallel input
setup and hold time increases by 60ps if the duty cycle is between 48% to 52% in 311MHz mode (Figure 1).
Relative to the falling edge of the SCLKO.
Measurement bandwidth is BW = 12kHz to 20MHz.
Measured with 00001111 pattern, RCLK to PCLKI/PDI[3:0] phase approximately 40ps. See the
Jitter Generation vs. RCLK to
PCLK/PDI[3:0] Phase
plot in the
Typical Operating Characteristics
section.
Deterministic jitter includes pattern-dependent jitter and pulse-width distortion. Measured using a 2
7
- 1 PRBS pattern with
96 consecutive identical digits.
4
_______________________________________________________________________________________
+3.3V, 2.5Gbps/2.7Gbps, SDH/SONET 4:1
Serializer with Clock Synthesis
Typical Operating Characteristics
(V
CC
= +3.3V, CML loads AC-coupled to 50Ω ±1%, T
A
= +25°C, unless otherwise noted.)
SUPPLY CURRENT vs. TEMPERATURE
MAX3892 toc01
MAX3892
ELECTRICAL EYE DIAGRAM
MAX3892 toc02
POWER-SUPPLY JITTER GENERATION
vs. RIPPLE FREQUENCY
35
JITTER GENERATION (ps
P-P
)
30
25
20
15
10
5
0
50mV
P-P
100mV
P-P
MAX3892 toc03
170
165
160
SUPPLY CURRENT (mA)
155
150
145
140
135
130
125
120
-40
-20
0
20
40
60
80
40
PATTERN 2
13
-1 PRBS
DATA RATE = 2.5Gbps
100
50ps/div
10
100
1k
10k
TEMPERATURE (°C)
RIPPLE FREQUENCY (kHz)
JITTER GENERATION vs. POWER SUPPLY
NOISE AMPLITUDE (BW = 2MHz)
MAX3892 toc04
JITTER GENERATION
vs. RCLK to PCLKI/PDI[3:0] PHASE
MAX3892 toc05
SERIAL-DATA OUTPUT JITTER
MAX3892 toc06
5.0
4.5
JITTER GENERATION (ps
RMS
)
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
0
50
100
150
200
1.4
PATTERN = 00001111
1.2
JITTER GENERATION (ps
RMS
)
1.0
0.8
0.6
0.4
0.2
0
f
RCLK
= 622MHz
250
0
50
100 150 200 250 300 350 400
NOISE AMPLITUDE (V
P-P
)
RCLK TO PCLKI/PDI[3:0] PHASE (ps)
5ps/div
TOTAL WIDEBAND RMS JITTER = 1.3ps
PEAK-TO-PEAK JITTER = 15.8ps
Pin Description
PIN
1, 16, 22, 27,
33, 44
2, 5, 8, 11
3
4
6
7
NAME
GND
VCCO
SCLKO-
SCLKO+
SDO-
SDO+
Supply Ground
Supply Voltage for Outputs +3.3V. Add bypass capacitors near these pins before connecting to
the V
CC
power plane.
Negative Serial Clock Output, CML 2.488GHz or 2.666GHz
Positive Serial Clock Output, CML 2.488GHz or 2.666GHz
Negative Serial Data Output, CML 2.488Gbps or 2.666Gbps
Positive Serial Data Output, CML 2.488Gbps or 2.666Gbps
FUNCTION
_______________________________________________________________________________________
5
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