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25AA080B-I-WF15K

产品描述EEPROM 8K, 1K X 8, 32B PAGE, 1.8V SER EE, WAFER on FRAME
产品类别存储   
文件大小787KB,共44页
制造商Microchip(微芯科技)
官网地址https://www.microchip.com
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25AA080B-I-WF15K概述

EEPROM 8K, 1K X 8, 32B PAGE, 1.8V SER EE, WAFER on FRAME

25AA080B-I-WF15K规格参数

参数名称属性值
产品种类
Product Category
EEPROM
制造商
Manufacturer
Microchip(微芯科技)
Memory Size8 kbit
Organization1 k x 8

文档预览

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25AA010A/25LC010A
25AA020A/25LC020A
25AA040A/25LC040A
25AA080A/25LC080A
25AA080B/25LC080B
25AA160A/25LC160A
25AA160B/25LC160B
25AA320A/25LC320A
25AA640A/25LC640A
25AA128/25LC128
25AA256/25LC256
25AA512/25LC512
25AA1024/25LC1024
SPI Serial EEPROM Family Data Sheet
Features:
• Max Clock Speed
- 10 MHz (1K-256K)
- 20 MHz (512K-1M)
• Byte and Page-level Write Operations
• Low-power CMOS Technology
- Typical Write current:
5 mA
- Typical Read current:
5 mA @ 10 MHz
7 mA @ 20 MHz
- Typical Standby current: 1
μA
• Write Cycle Time: 5 ms max.
6 ms max. (25XX1024)
• Self-timed Erase and Write Cycles
• Erase Functions (512K-1M)
- Page Erase: 6 ms max.
- Sector Erase: 15 ms max.
- Chip Erase: 15 ms max.
• Built-in Write Protection
- Power on/off data protection circuitry
- Write enable latch
- Write-protect pin
• Block/Sector Write Protection
- Protect none, 1/4, 1/2 or all of array
• Sequential Read
• High Reliability
- Data retention: > 200 years
- ESD protection: > 4000V
- Endurance > 1M Erase/Write Cycles
• Available in Standard 8-pin and 6-pin Packages
• Temperature Ranges Supported:
- Industrial (I): -40°C to +85°C
- Automotive (E): -40°C to +125°C
Pin Function Table
Name
CS
SO
WP
V
SS
SI
SCK
HOLD
V
CC
Chip Select
Serial Data Output
Write-Protect
Ground
Serial Data Input
Serial Clock Input
Hold Input
Supply Voltage
CS 1
SO 2
WP 3
V
SS
4
Description:
Microchip Technology Inc. supports the Serial Periph-
eral Interface (SPI) compatible serial bus architecture
with low-voltage serial Electrically Erasable PROMs
(EEPROM) that range in density from 1 Kbits up to 1
Mbits. Byte-level and page-level functions are sup-
ported, but the higher density 512 Kbit and 1 Mbit
devices also feature Sector and Chip erase functions
typically associated with Flash-based products.
The bus signals required are a clock input (SCK) plus
separate data in (SI) and data out (SO) lines. Access to
the device is controlled through a Chip Select (CS)
input.
Communication to the device can be paused via the
hold pin (HOLD). While the device is paused, transi-
tions on its inputs will be ignored, with the exception of
Chip Select, allowing the host to service higher priority
interrupts.
The entire series of SPI compatible devices are avail-
able in the standard 8-lead PDIP and SOIC pack-
ages, as well as the more advanced packages such
as the 8-lead TSSOP, MSOP, 2x3 DFN, 5x6 DFN and
6-lead SOT-23. All packages are RoHS compliant
with a Pb-free (Matte Tin) finish.
Pin Diagrams (not to scale)
TSSOP/MSOP
(ST, MS)
CS
SO
WP
V
SS
1
2
3
4
8
7
6
5
V
CC
HOLD
SCK
SI
PDIP/SOIC
(P, SN, SM)
CS
SO
WP
V
SS
1
2
3
4
8
7
6
5
V
CC
HOLD
SCK
SI
SOT-23
(OT)
SCK
V
SS
SI
1
2
3
6
5
4
V
DD
CS
SO
DFN
(MC)
CS 1
SO 2
WP 3
V
SS
4
8 V
CC
7 HOLD
6 SCK
5 SI
Function
DFN
(MF)
8
7
6
5
V
CC
HOLD
SCK
SI
©
2007 Microchip Technology Inc.
Preliminary
DS22040A-page 1

 
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