Frequency Generator/Jitter Attenuation Device
For Wireless Infrastructure Applications
G
ENERAL
D
ESCRIPTION
The ICS813076I is a member of the HiperClocks family of high
performance clock solutions from IDT. The ICS813076I a PLL
based synchronous clock solution that is optimized for wireless
infrastructure equipment where frequency translation and jitter
attenuation is needed.
The device contains two internal PLL stages that are cascaded
in series. The first PLL stage attenuates the reference clock
jitter by using an internal or external VCXO circuit. The internal
VCXO requires the connection of an external inexpensive pullable
crystal (XTAL) to the ICS813076I. This first PLL stage (VCXO
PLL) uses external passive loop filter components which are used
to optimize the PLL loop bandwidth and damping characteristics
for the given application. The output of the first stage VCXO
PLL is a stable and jitter-tolerant reference input for the second
PLL stage of 30.72MHz. The second PLL stage provides
frequency translation by multiplying the output of the first stage
up to 614.4MHz. The low phase noise characteristics of the clock
signal is maintained by the internal FemtoClock™ PLL, which
requires no external components or configuration. Two independently
configurable frequency dividers translate the 491.52MHz or
614.4MHz internal VCO signal to the desired output frequencies.
All frequency translation ratios are set by device configuration pins.
Alternative to the clock frequency multiplication functionality, the
ICS813076I can work as a VCXO. Enabling the VCXO mode allows
the output frequency of 614.4MHz/N or 491.52MHz/N to be pulled
by the input voltage of the VC pin.
•
Supported input reference clock frequencies:
15.36MHz,
30.72MHz
61.44MHz
•
Supported output clock frequencies:
30.72MHz
122.88MHz
153.6MHz
491.52MHz
614.4MHz
813076
OBSOLETE
DATASHEET
F
EATURES
•
Two operation modes: input frequency multiplier and VCXO
•
Nine differential LVPECL outputs, organized in three indepen-
dent output banks
•
Two selectable differential input clocks can accept the following
differential input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL
•
Maximum output frequency: 614.4MHz
•
FemtoClock VCO frequency: 491.52MHz or 614.4MHz (typical)
•
Frequency generation optimized for wireless infrastructure equip-
ment
•
Attenuates the phase jitter of the input clock signal by using a
low-cost pullable fundamental mode crystal (XTAL)
•
Multiplies the input clock frequency by 1, 4, 5, 16 or 20
•
LVCMOS/LVTTL levels for all input/output controls
•
PLL fast-lock control
•
VCXO PLL bandwidth can be optimized for jitter attenuation
and reference frequency tracking using external loop filter
components
•
Absolute pull range: ±50ppm
•
RMS phase jitter (12kHz – 20MHz): 0.97ps (typical)
•
Full 3.3V supply
•
-40°C to 85°C ambient operating temperature
•
Available in lead-free (RoHS 6) package
•
For functional replacement device use 8T49N286-dddNLGI
P
IN
A
SSIGNMENT
LF1
LF0
ISET
VC
FLM
V
CC
V
CC
CLK1
nCLK1
nMR
CLK0
nCLK0
V
EE
LOCK
V
CCO
NA_SEL1
64 63 62 6160 59 58 57 56 55 54 53 52 51 50 49
1
2
3
4
5
6
7
64-Lead TQFP, E-Pad
8
10mm x 10mm x 1.0mm
9
package body
10
Y package
11
Top View
12
13
14
15
16
nQA0
QA0
V
CCO
nQC
QC
V
CCO
V
EE
nc
nc
MF_SEL
MV_SEL
VC_SEL
V
CC
XTAL_OUT
XTAL_IN
V
EE
813076I
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
nQA1
QA1
V
CCO
nQA2
QA2
V
EE
nQA3
QA3
V
CCO
nQA4
QA4
V
CC
V
EE
nQB0
QB0
V
CCO
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
nQB1
QB1
V
CCO
nQB2
QB2
V
CCA
nc
REF_SEL
nSTOP
nBYPASS
P
NC_SEL0
NC_SEL1
NB_SEL0
NB_SEL1
NA_SEL0
813076 REVISION B 7/29/16
1
©2016 Integrated Device Technology, Inc.
813076 DATA SHEET
B
LOCK
D
IAGRAM
30.72MHz
XTAL_IN
XTAL_OUT
ISET
LF1
LF0
LOCK
QA0
÷NA
nQA0
QA4
nQA4
0
CLK0
nCLK0
CLK1
nCLK1
P_SEL
VC
VC_SEL
Pulldown
Pulldown
Pullup/Pulldown
Pulldown
Pullup/Pulldown
QB0
0
1
÷P
f
PD
PD
CP
0
1
÷NB
VCXO
f
VCXO
Femto f
VCO
PLL
nQB0
QB1
nQB1
QB2
1
Pulldown
÷MF
nQB2
Multiplier / Divider
÷NC
÷MV
Internal VCXO
QC
nQC
MV_SEL
MF_SEL
REF_SEL
nBYPASS
NA_SEL[1:0]
NB_SEL[1:0]
NC_SEL[1:0]
FLM
nMR
nSTOP
Pulldown
Pulldown
Pulldown
Pullup
Pulldown
Pulldown
Pulldown
Pulldown
Pullup
Pullup
FREQUENCY GENERATOR/JITTER ATTENUATION DEVICE FOR
WIRELESS INFRASTRUCTURE APPLICATIONS
2
REVISION B 7/29/16
813076 DATA SHEET
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1
2
3
4
5
6, 7, 37, 61
8
9
10
11
12
13, 36, 43, 55,
64
14
15, 30, 33, 40,
46, 51, 54
16,
17
18,
19
20,
21
22
23
24
25
26, 56, 57
27
28, 29
31, 32
34, 35
38, 39
41, 42
44, 45
47, 48
49, 50
52, 53
58
59
60
62,
63
Name
LF1
LF0
ISET
VC
FLM
V
CC
CLK1
nCLK1
nMR
CLK0
nCLK0
V
EE
LOCK
V
CCO
NA_SEL1,
NA_SEL0
NB_SEL1,
NB_SEL0
NC_SEL1,
NC_SEL0
P_SEL
nBYPASS
nSTOP
REF_SEL
nc
V
CCA
QB2, nQB2
QB1, nQB1
QB0, nQB0
QA4, nQA4
QA3, nQA3
QA2, nQA2
QA1, nQA1
nQA0, QA0
nQC, QC
MF_SEL
MV_SEL
VC_SEL
XTAL_OUT,
XTAL_IN
Analog
Input
Analog
Output
Analog
Analog
Input
Power
Input
Input
Input
Input
Input
Power
Output
Power
Input
Input
Input
Input
Input
Input
Input
Unused
Power
Output
Pulldown
Pulldown
Pulldown
Pulldown
Pullup
Pullup
Pulldown
Pulldown
Pullup/
Pulldown
Pullup
Pulldown
Pullup/
Pulldown
Pulldown
Type
Description
Input from external loop filter. VCXO control voltage input.
Output to external loop filter. Charge pump output.
Charge pump current setting pin.
Control voltage to the VCXO.
VCXO-PLL fast lock mode. LVCMOS/LVTTL interface levels. See Table 3H.
Core power supply pins.
Non-inverting differential reference clock input.
Inverting differential clock input. V
CC
/2 bias voltage when left floating.
Master reset pin. LVCMOS/LVTTL interface levels. See Table 3I.
Non-inverting differential reference clock input.
Inverting differential clock input. V
CC
/2 bias voltage when left floating.
Negative supply pins.
VCXO-PLL lock state. In VCXO-PLL mode (VC_SEL = 0), logic HIGH at the
LOCK output indicates frequency lock of the VCXO-PLL. In VCXO-PLL mode
(VC_SEL = 1), the state of LOCK is always 0. LVCMOS/LVTTL interface levels.
Output supply pins.
FemtoPLL output-divider for QA outputs. LVCMOS/LVTTL interface levels.
See Table 3F.
FemtoPLL output-divider for QB outputs. LVCMOS/LVTTL interface levels.
See Table 3F.
FemtoPLL output-divider for QC outputs. LVCMOS/LVTTL interface levels.
See Table 3F.
VCXO pre-divider selection. LVCMOS/LVTTL interface levels. See Table 3B.
PLL mode selection. LVCMOS/LVTTL interface levels. See Table 3G.
Ouput clock stop pin. LVCMOS/LVTTL interface levels. See Table 3J.
Selects the input reference clock. LVCMOS/LVTTL interface levels.
See Table 3E.
No connect.
Analog supply pin.
Differential Bank B clock outputs. LVPECL interface levels.
Output
Differential Bank A clock outputs. LVPECL interface levels.
Output
Input
Input
Input
Input
Pulldown
Pulldown
Pulldown
Differential Bank C clock outputs. LVPECL interface levels.
Femto-PLL feedback divider selection. LVCMOS/LVTTL interface levels.
See Table 3D.
VCXO M-divider selection. LVCMOS/LVTTL interface levels. See Table 3C.
Controls the mode of operation. LVCMOS/LVTTL interface levels.
See Table 3K.
VCXO crystal oscillator interface. XTAL_IN is the input.
XTAL_OUT is the output.
NOTE:
Pulldown and Pullup
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
REVISION B 7/29/16
3
FREQUENCY GENERATOR/JITTER ATTENUATION DEVICE
FOR WIRELESS INFRASTRUCTURE APPLICATIONS
813076 DATA SHEET
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
kΩ
kΩ
D
EVICE
C
ONFIGURATION
The ICS813076I is a two stage device, a VCXO PLL stage followed
by a low phase noise FemtoClock PLL multiplier stage. The VCXO
PLL stage uses a pullable crystal to lock to the reference clock. The
low phase noise FemtoClock multiplies the VCXO PLL output clock
up to 614.4MHz and three independent output dividers scale the
frequency down to the desired output frequencies. With a given input
and VCXO frequency, the output frequency is a function of the P, MV,
MF and NA, NB, NC dividers, and can be set by pulling configuration
pins high or low. See “ICS813076I Examples Frequency Con-
figuration (f
VCXO
= 30.72MHz)” for typical device configurations. Note
that for correct operation, the input frequency times the MV-divider
must be 30.72MHz ± 50ppm. The ICS813076I supports up to three
output frequencies f
OUT
independently.
T
ABLE
3A. F
REQUENCY
C
ONFIGURATION
E
XAMPLES
T
ABLE
(f
VCXO
= 30.72MH
Z
)
f
IN
(MHz)
30.72
30.72
30.72
30.72
30.72
30.72
30.72
30.72
f
OUT
(MHz)
30.72
122.8
153.6
614.4
24.576
98.304
122.8
491.52
Ratio
1
4
5
20
4/5
16/5
4
16
Configuration
P
1
1
1
1
1
1
1
1
MV
1
1
1
1
1
1
1
1
MF
20
20
20
20
16
16
16
16
NA, NB, NC
20
5
4
1
20
5
4
1
NOTE: The example frequency configuration table is intended to show the most common fre-
quency translations. The following example will illustrate the configuration process.
30.72MHz
XTALIN
XTALOUT
CLK
P=1
30.72MHz
VCXO
MV = 1
FemtoClock PLL
VCO = 614.4MHz
MF = 20
Qn
N=4
153.6MHz
ICS813076I
F
IGURE
1. A
PPLICATION
E
XAMPLE
(153.6MH
Z
C
LOCK
G
ENERATION AND
J
ITTER
A
TTENUATION
)
FREQUENCY GENERATOR/JITTER ATTENUATION DEVICE FOR
WIRELESS INFRASTRUCTURE APPLICATIONS
4
REVISION B 7/29/16
813076 DATA SHEET
The VCXO pre-divider (P) down-scales the input reference
frequency f
REF
and enables the use of the ICS813076I at a variety
of input frequencies. P_SEL and MV_SEL must be set to match the
VCXO frequency: f
REF
÷ P = f
VCXO
÷ MV. For instance, at the nominal
VCXO frequency of 30.72MHz and if MV equals two, the input
frequency must be an integer multiple of 15.36MHz.
T
ABLE
3B. VCXO P
RE
-D
IVIDER
(P) C
ONFIGURATION
T
ABLE
Input
P_SEL
0
1
Pre-Divider Function
÷1
÷2
Operation
f
PD
= f
REF
÷ 1
f
PD
= f
REF
÷ 2
T
ABLE
3C. VCXO M
ULTIPLIER
(MV-D
IVIDER
) C
ONFIGURATION
T
ABLE
Input
MV_SEL
0
1
Multiplier MV Function Operation
1
2
f
VCXO
= f
PD
f
VCXO
= f
PD
* 2
T
ABLE
3D. F
EMTO
C
LOCK
F
EEDBACK
D
IVIDER
(MF)
C
ONFIGURATION
T
ABLE
Input
MF_SEL
0
1
Multiplier MF Function Operation
20
16
f
VCO
= f
VCXO
* 20
f
VCO
= f
VCXO
* 16
T
ABLE
3E. I
NPUT
R
EFERENCE
C
LOCK
M
ULTIPLEXER
C
ONFIGURATION
T
ABLE
Input
REF_SEL
0 (default)
1
Operation
Selects CLK0, nCLK0 as PLL reference signal
Selects CLK1, nCLK1 as PLL reference signal
T
ABLE
3F. PLL O
UTPUT
-D
IVIDER
(NA, NB, NC) C
ONFIGURATION
T
ABLE
Inputs
Nx_SEL1
0
0
1
1
Nx_SEL0
0
1
0
1
Output Dividers
NA, NB, NC
÷1
÷4
÷5
÷20
Operation
f
OUT
= f
VCO
f
OUT
= f
VCO
÷ 4
f
OUT
= f
VCO
÷ 5
f
OUT
= f
VCO
÷ 20
The FemtoClock PLL stage multiplies the VCXO frequency (30.72MHz) to
491.52MHz or 614.4MHz. The output frequency equals:
[(f
REF
÷ P) * MV * MF] ÷ N. The NA, NB and NC dividers operate independently.
T
ABLE
3G. PLL B
YPASS
C
ONFIGURATION
T
ABLE
Input
nBYPASS
0
1 (default)
Operation
f
OUT
= f
REF
÷ N
VCXO and PLL bypassed, no jitter attenuation and frequency multiplication. AC specifications do not apply.
((f
REF
÷ P) * MV * MF) ÷ N
VCXO and PLL operation, jitter attenuation and frequency multiplication enabled.
The nBYPASS control should be set to logic HIGH for normal operation. nBYPASS = 0 enables the PLL bypass mode for factory test.
REVISION B 7/29/16
5
FREQUENCY GENERATOR/JITTER ATTENUATION DEVICE
FOR WIRELESS INFRASTRUCTURE APPLICATIONS
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