NB3N200S
3.3 V Differential Multipoint
Low Voltage M-LVDS Driver
Receiver
Description
The NB3N200 is a pure 3.3 V supply differential Multipoint Low
Voltage (M−LVDS) line Driver and Receiver. NB3N200S is
TIA/EIA−899 compliant. NB3N200S offers the Type 1 receiver
threshold at 0.0 V.
These devices has a Type−1 receiver that detect the bus state with as
little as 50 mV of differential input voltage over a common−mode
voltage range of −1 V to 3.4 V. The Type−1 receivers have near zero
thresholds (±50 mV) and exhibit 25 mV of differential input voltage
hysteresis to prevent output oscillations with slowly changing signals
or loss of input.
NB3N200S supports Simplex or Half Duplex bus configurations.
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MARKING
DIAGRAM
1
SOIC−8
D SUFFIX
CASE 751
8
NB20x
AYWW
G
1
8
NB20x
x
A
Y
WW
G or
G
= Specific Device Code
= 0, 2, 4, 5
= Assembly Location
= Year
= Work Week
= Pb−Free Package
Features
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 17 of this data sheet.
•
Low−Voltage Differential 30
W
to 55
W
Line Drivers and Receivers
•
•
•
•
•
•
•
•
for Signaling Rates Up to 200 Mbps
Type−1 Receivers Incorporate 25 mV of Hysteresis
Meets or Exceeds the M−LVDS Standard TIA/EIA−899
for Multipoint Data Interchange
Controlled Driver Output Voltage Transition Times for
Improved Signal Quality
−1 V to 3.4 V Common−Mode Voltage Range Allows
Data Transfer With up to 2 V of Ground Noise
Bus Pins High Impedance When Disabled or V
CC
≤
1.5 V
M−LVDS Bus Power Up/Down Glitch Free
Operating range: V
CC
= 3.3
±10%
V( 3.0 to 3.6 V)
Operation from –40°C to 85°C.
•
Pb−Free SOIC 8 Package
•
These are Pb−Free Devices
Applications
•
Low−Power High−Speed Short−Reach Alternative to
•
•
•
•
TIA/EIA−485
Backplane or Cabled Multipoint Data and Clock
Transmission
Cellular Base Stations
Central−Office Switches
Network Switches and Routers
Figure 1. Logic Diagrams
©
Semiconductor Components Industries, LLC, 2015
1
June, 2015 − Rev. 1
Publication Order Number:
NB3N200S/D
NB3N200S
R
RE
1
8 V
CC
7 B
2
DE
3
6 A
D
4
SOIC−8
NB3N200S
5 GND
Figure 2. Pinout Diagrams
(Top View)
Table 1. PIN DESCRIPTION SOIC−8
Number
1
2
3
4
5
6
7
8
Name
R
RE
DE
D
GND
A
B
VCC
M−LVDS Input /
Output
M−LVDS Input /
Output
I/O Type
LVCMOS Output
LVCMOS Input
LVCMOS Input
LVCMOS Input
High
Low
Open Default
Receiver Output Pin
Receiver Enable Input Pin (LOW = Active, HIGH = High Z
Output)
Driver Enable Input Pin (LOW = High Z Output, HIGH = Active)
Driver Output Pin
Ground Supply pin. Pin must be externally connected to power
supply to guarantee proper operation.
Transceiver Invert Input / Output Pin
Transceiver True Input / Output Pin
Power Supply pin. Pin must be externally connected to power
supply to guarantee proper operation.
Description
Table 2. DEVICE FUNCTION TABLE
Inputs
V
ID
= V
A
− V
B
V
ID
w
50 mV
TYPE 1 Receiver (NB3N200)
−50 mV < V
ID
< 50 mV
V
ID
≤
−50 mV
X
X
Open
Input
D
L
DRIVER
H
Open
X
X
RE
L
L
L
H
Open
L
Enable
DE
H
H
H
Open
L
A/Y
L
H
L
Z
Z
Output
R
H
?
L
Z
Z
?
Output
B/Z
H
L
H
Z
Z
H = High, L = Low, Z = High Impedance, X = Don’t Care, ? = Indeterminate
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2
NB3N200S
Table 3. ATTRIBUTES
(Note 1)
Characteristics
Internal Input Pullup Resistor
Internal Input Pulldown Resistor
Human Body Model (JEDEC
Standard 22, Method A114−A)
ESD
Protection
Machine Model
Charged –Device Model (JEDEC
Standard 22, Method C101)
A, B, Y, Z
All Pins
All Pins
All Pins
Value
50 kW
50 kW
±6
kV
±2
kV
±200
V
±1500
V
Level 1
UL−94 V−0 @ 0.125 in
28 to 34
917 Devices
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)
Flammability Rating
Oxygen Index
Transistor Count
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
Table 4. MAXIMUM RATINGS
(Note 2)
Symbol
V
CC
V
IN
Supply Voltage
Input Voltage
D, DE, RE
A, B (200, 204)
A, B (202, 205)
I
OUT
Parameter
Condition 1
Condition 2
Rating
−0.5
≤
V
CC
≤
4.0
−0.5
≤
V
IN
≤
4.0
−1.8
≤
V
IN
≤
4.0
−4.0
≤
V
IN
≤
6.0
−0.3
≤
I
OUT
≤
4.0
−1.8
≤
I
OUT
≤
4.0
−40 to
≤
+85
−65 to +150
Unit
V
V
Output Voltage
Operating Temperature Range, Industrial
Storage Temperature Range
Thermal Resistance (Junction−to−Ambient)
Thermal Resistance (Junction−to−Case)
Wave Solder
Power Dissipation (Continuous)
R
Y, Z, A, B
V
°C
°C
°C/W
°C/W
°C/W
°C
mW
mW/°C
mW
T
A
T
stg
θ
JA
θ
JC
T
sol
P
D
0 lfpm
500 lfpm
(Note 3)
SOIC−8
SOIC−8
190
130
41 to 44
265
SOIC−8
T
A
= 25°C
25°C < T
A
< 85°C
T
A
= 85°C
725
5.8
377
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
2. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and not valid simultaneously.
If stress limits are exceeded device functional operation is not implied, damage may occur and reliability may be affected.
3. JEDEC standard multilayer board − 2S2P (2 signal, 2 power).
Table 5. DC CHARACTERISTICS
VCC = 3.3
±10%
V( 3.0 to 3.6 V), GND = 0 V, T
A
= −40°C to +85°C (See Notes 4, 5)
Symbol
ICC
Characteristic
Power Supply Current
Receiver Disabled Driver Enabled RE and DE at V
CC
, R
L
= 50
W,
All others open
Driver and Receiver Disabled RE at VCC, DE at 0 V, R
L
= No Load, All others open
Driver and Receiver Enabled RE at 0 V, DE at V
CC
, R
L
= 50
W,
All others open
Receiver Enabled Driver Disabled RE at 0 V, DE at 0 V, R
L
= 50
W,
All others open
Input HIGH Voltage
Input LOW Voltage
Voltage at any bus terminal VA, VB, VY or VZ
Magnitude of differential input voltage
2
GND
−1.4
0.05
Min
Typ
13
1
16
Max
22
4
24
13
V
CC
0.8
3.8
V
CC
V
V
V
Unit
mA
V
IH
V
IL
VBUS
|VID|
DRIVER
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NB3N200S
Table 5. DC CHARACTERISTICS
VCC = 3.3
±10%
V( 3.0 to 3.6 V), GND = 0 V, T
A
= −40°C to +85°C (See Notes 4, 5)
Symbol
DRIVER
|V
AB
| /
|V
YZ
|
D|V
AB
| /
D|V
YZ
|
V
OS(SS)
DV
OS(SS)
V
OS(PP)
V
YOC
/
V
AOC
V
ZOC
/
V
BOC
V
P(H)
V
P(L)
I
IH
I
IL
JI
OS
J
I
OZ
I
O(OFF)
C
Y
/ C
Z
C
YZ
C
Y/Z
RECEIVER
V
IT+
Positive−going Differential Input voltage Threshold (See Figure 11 & Table 8)
Type 1
Type 2
V
IT−
Negative−going Differential Input voltage Threshold (See Figure 11 & Table 8)
Type 1
Type 2
V
HYS
Differential Input Voltage Hysteresis (See Figure 11 and Table 2)
Type 1
Type 2
VOH
VOL
I
IH
I
IL
I
OZ
C
A
/ C
B
C
AB
C
A/B
High−level output voltage (IOH = –8 mA
Low−level output voltage (IOL = 8 mA)
RE
High-level
input current (VIH = 2 V)
RE
Low-level
input current (VIL = 0.8 V)
High−impedance state output current (VO = 0 V of 3.6 V)
Input Capacitance VI = 0.4 sin(30E
6
πt)
+ 0.5 V, other outputs at 1.2 V using HP4194A
impedance analyzer (or equivalent)
Differential Input Capacitance V
AB
= 0.4 sin(30E
6
πt)
V, other outputs at 1.2 V using
HP4194A impedance analyzer (or equivalent)
Input Capacitance Balance, (C
A
/C
B
)
99
2.4
−10
−10
−10
3
2.5
101
0.4
0
0
15
25
0
V
V
mA
mA
mA
pF
pF
%
−50
50
mV
50
150
mV
mV
Differential output voltage magnitude (see Figure 4)
Change in Differential output voltage magnitude between logic states (see Figure 4)
Steady state common mode output voltage (see Figure 5)
Change in Steady state common mode output voltage between logic states (see
Figure 5)
Peak−to−peak common−mode output voltage (see Figure 5)
Maximum steady−state open−circuit output voltage (see Figure 9)
Maximum steady−state open−circuit output voltage (see Figure 9)
Voltage overshoot, low−to−high level output (see Figure 7)
Voltage overshoot, high−to−low level output (see Figure 7)
High−level input current (D, DE) V
IH
= 2 V
Low−level input current (D, DE) V
IL
= 0.8 V
Differential short−circuit output current magnitude (see Figure 6)
High−impedance state output current (driver only)
−1.4 V
≤
(VY or VZ)
≤
3.8 V, other output at 1.2 V
Power−off output current (0 V
≤
V
CC
≤
1.5 V)
−1.4 V
≤
(VY or VZ)
≤
3.8 V, other output at 1.2 V
Output Capacitance VI = 0.4 sin(30E
6
πt)
+ 0.5 V, other outputs at 1.2 V using
HP4194A impedance analyzer (or equivalent)
Differential Output Capacitance V
AB
= 0.4 sin(30E
6
pt)
V, other outputs at 1.2 V using
HP4194A impedance analyzer (or equivalent)
Output Capacitance Balance, (C
Y
/C
Z
)
99
480
−50
0.8
−50
650
50
1.2
50
150
2.4
2.4
1.2 V
SS
−0.2 V
SS
0
0
−15
−10
3
2.5
101
10
10
24
10
10
mV
mV
V
mV
mV
V
V
V
V
uA
uA
mA
uA
uA
pF
pF
%
Characteristic
Min
Typ
Max
Unit
0
0
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NB3N200S
Table 5. DC CHARACTERISTICS
VCC = 3.3
±10%
V( 3.0 to 3.6 V), GND = 0 V, T
A
= −40°C to +85°C (See Notes 4, 5)
Typ
(Note
5)
Symbol
BUS INPUT AND OUTPUT
I
A
Characteristic
Min
Max
Unit
Input Current Receiver or Transceiver with Driver Disabled
V
A
= 3.8 V, V
B
= 1.2 V
V
A
= 0.0 V or 2.4 V, V
B
= 1.2 V
V
A
= −1.4 V, V
B
= 1.2 V
0
−20
−32
0
−20
−32
−4
0
−20
−32
0
−20
−32
−4
5
5
3.0
32
20
0
uA
I
B
Input Current Receiver or Transceiver with Driver Disabled
V
B
= 3.8 V, V
A
= 1.2 V
V
B
= 0.0 V or 2.4 V, V
A
= 1.2 V
V
B
= −1.4 V, V
A
= 1.2 V
32
20
0
uA
I
AB
I
A(OFF)
Differential Input Current Receiver or Transceiver with driver disabled (I
A
−I
B
)
V
A
= V
B
, −1.4
≤
V
A
≤
3.8 V
Input Current Receiver or Transceiver Power Off 0V
≤
V
CC
≤
1.5 and:
V
A
= 3.8 V, V
B
= 1.2 V
V
A
= 0.0 V or 2.4 V, V
B
= 1.2 V
V
A
= −1.4 V, V
B
= 1.2 V
Input Current Receiver or Transceiver Power Off 0V
≤
V
CC
≤
1.5 and:
V
B
= 3.8 V, V
A
= 1.2 V
V
B
= 0.0 V or 2.4 V, V
A
= 1.2 V
V
B
= −1.4 V, V
A
= 1.2 V
Receiver Input or Transceiver Input/Output Power Off Differential Input Current; (I
A
−I
B
)
V
A
= V
B
, 0
≤
V
CC
≤
1.5 V, −1.4
≤
V
A
≤
3.8 V
Transceiver Input Capacitance with Driver Disabled V
A
= 0.4
HP4194A impedance analyzer (or equivalent); V
B
= 1.2 V
sin(30E
6
πt)
+ 0.5 V using
uA
4
uA
32
20
0
uA
32
20
0
uA
4
pF
pF
pF
I
B(OFF)
I
AB(OFF)
C
A
C
B
C
AB
Transceiver Input Capacitance with Driver Disabled V
B
= 0.4 sin(30E
6
πt)
+ 0.5 V using
HP4194A impedance analyzer (or equivalent); V
A
= 1.2 V
Transceiver Differential Input Capacitance with Driver Disabled V
A
= 0.4 sin(30E
6
pt)
+
0.5 V using HP4194A impedance analyzer (or equivalent);
V
B
= 1.2 V
Transceiver Input Capacitance Balance with Driver Disabled, (C
A
/C
B
)
99
C
A/B
101
%
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm.
4. See Figure 3. DC Measurements reference.
5. Typ value at 25°C and 3.3 VCC supply voltage.
Table 6. DRIVER AC CHARACTERISTICS
VCC = 3.3
±10%
V( 3.0 to 3.6 V), GND = 0 V, T
A
= −40°C to +85°C (Note 6)
Symbol
t
PLH
/ t
PHL
t
PHZ
/ t
PLZ
t
PZH
/ t
PZL
t
SK(P)
t
SK(PP)
t
JIT(PER)
t
JIT(PP)
Characteristic
Propagation Delay (See Figure 7)
Disable Time HIGH or LOW state to High Impedance (See Figure 8)
Enable Time High Impedance to HIGH or LOW state (See Figure 8)
Pulse Skew (|t
PLH
− t
PHL
|) (See Figure 7)
Device to Device Skew similar path and conditions (See Figure 7)
Period Jitter RMS, 100 MHz (Source tr/tf 0.5 ns, 10 and 90 % points, 30k sam-
ples. Source jitter de−embedded from Output values ) (See Figure 10)
Peak−to−peak Jitter, 200 Mbps 2
15
−1 PRBS (Source tr/tf 0.5 ns, 10 and 90%
points, 100k samples. Source jitter de−embedded from Output values) (See
Figure 10)
Differential Output rise and fall times (See Figure 7)
1
0
Min
1.0
Typ
Max
2.4
7
7
150
0.9
3
150
Unit
ns
ns
ns
ps
ns
ps
ps
tr / tf
1.6
ns
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm.
6. Typ value at 25°C and 3.3 V
CC
supply voltage.
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