CY2077
High-Accuracy One-Time Programmable
Single-PLL Clock Generator
High-Accuracy One-Time Programmable Single-PLL Clock Generator
Features
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Sixteen selectable post-divide options, using either PLL or
reference oscillator/external clock
Programmable PWR_DWN or OE pin, with asynchronous or
synchronous modes
Low jitter outputs typically
❐
80 ps at 3.3 V/5 V
Controlled rise and fall times and output slew rate
Available in both commercial and industrial temperature ranges
Factory programmable device options
High-accuracy PLL with 12-bit multiplier and 10-bit divider
One-time programmability
3.3 V or 5 V operation
Operating frequency
❐
390 kHz–133 MHz at 5 V
❐
390 kHz–100 MHz at 3.3 V
Reference input from either a 10 MHz–30 MHz fundamental
toned crystal or a 1 MHz–75 MHz external clock
PROM selectable TTL or CMOS duty cycle levels
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Functional Description
For a complete list of related documentation, click
here.
Logic Block Diagram
PWR_DWN
or OE
Phase Detector
Crystal
Oscillator
Charge
Pump
Configuration
PROM
XTALOUT
[1]
Q
10 bits
XTALIN
or
external clock
VCO
P
12 bits
HIGH
ACCURACY
PLL
MUX
/ 1, 2, 4, 8, 16, 32, 64, 128
CLKOUT
Note
1. When using an external clock source, leave XTALOUT floating.
Cypress Semiconductor Corporation
Document Number: 38-07210 Rev. *J
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised June 7, 2017
CY2077
Contents
Pinouts .............................................................................. 3
Pin Definitions .................................................................. 3
Functional Overview ........................................................ 4
PROM Configuration Block ......................................... 4
PLL Output Frequency ................................................ 4
Power Management Features ..................................... 4
Absolute Maximum Ratings ............................................ 5
Operating Conditions ....................................................... 5
Electrical Characteristics ................................................. 6
Output Clock Switching Characteristics
- Commercial ..................................................................... 7
Operating Conditions ....................................................... 8
Electrical Characteristics ................................................. 9
Output Clock Switching Characteristics
- Industrial ....................................................................... 10
Switching Waveforms .................................................... 12
Typical Rise/Fall Time Trends ....................................... 13
Typical Duty Cycle Trends ............................................. 14
Typical Jitter Trends ...................................................... 15
Programming Procedures ............................................. 16
Ordering Information ...................................................... 16
Package Diagrams .......................................................... 17
Document History Page ................................................. 19
Sales, Solutions, and Legal Information ...................... 20
Worldwide Sales and Design Support ....................... 20
Products .................................................................... 20
PSoC® Solutions ...................................................... 20
Cypress Developer Community ................................. 20
Technical Support ..................................................... 20
Document Number: 38-07210 Rev. *J
Page 2 of 20
CY2077
Pinouts
Figure 1. 8-pin SOIC pinout (Top View)
V
DD
XTALOUT
XTALIN
PD/OE
1
2
3
4
8
7
6
5
CLKOUT
V
SS
V
SS
V
SS
Pin Definitions
8-pin SOIC
Pin Name
V
DD
V
SS
X
D
X
G
PWR_DWN / OE
CLKOUT
Pin
1
5, 6, 7
2
3
4
8
Voltage supply
Ground (all the pins must be grounded)
Crystal output (leave this pin floating when external reference is used)
Crystal input or external input reference
One-time programmable power-down or output enable pin. PWR_DWN is active low. OE is active
high. Weak pull-up.
Clock output. Weak pull-down
Pin Description
Document Number: 38-07210 Rev. *J
Page 3 of 20
CY2077
Functional Overview
CY2077 is an one-time programmable, high-accuracy,
general-purpose, PLL-based design for use in applications such
as modems, disk drives, CD-ROM drives, video CD players,
DVD
players,
games,
set-top
boxes,
and
data/telecommunications.
CY2077 can generate a clock output up to 133 MHz at 5 V or
100 MHz at 3.3 V. It has been designed to give the customer a
very accurate and stable clock frequency with little to zero PPM
error. CY2077 contains a 12-bit feedback counter divider and
10-bit reference counter divider to obtain a very high resolution
to meet the needs of stringent design specifications.
Furthermore, there are eight output divide options of /1, /2, /4, /8,
/16, /32, /64, and /128. The output divider can select between the
PLL and crystal oscillator output/external clock, providing a total
of 16 different options to add more flexibility in designs. TTL or
CMOS duty cycles can be selected.
Power management with the CY2077 is also very flexible. The
user can choose either a PWR_DWN, or an OE feature with
which both have integrated pull up resistors. PWR_DWN and OE
signals can be programmed to have asynchronous and
synchronous timing with respect to the output signal. There is a
weak pull down on the output that pulls CLKOUT LOW when
either the PWR_DWN or OE signal is LOW. This weak pull down
can easily be overridden by another clock signal in designs
where multiple clock signals share a signal path.
Multiple options for output selection, better power distribution
layout, and controlled rise and fall times enable the CY2077 to
be used in applications that require low jitter and accurate
reference frequencies.
PLL Output Frequency
CY2077 contains a high-resolution PLL with 12-bit multiplier and
10-bit divider
[2]
. The output frequency of the PLL is determined
by the following formula:
2
• (
P + 5
)
F
PLL
= ---------------------------
•
F
REF
(
Q + 2
)
where P is the feedback counter value and Q is the reference
counter value. P and Q are One-Time programmable values.
The calculation of P and Q values for a given PLL output
frequency is handled by the CyberClocks software. Refer to
Programming Procedures on page 16
for details.
Power Management Features
PWR_DWN and OE options are configurable by PROM
programming for the CY2077. In PWR_DWN mode, all active
circuits are powered down when the control pin is set LOW.
When the control pin is set back HIGH, both the PLL and
oscillator circuit must relock. In the case of OE, the output is
three-stated and weakly pulled down when the control pin is set
LOW. The oscillator and PLL are still active in this state, which
leads to a quick clock output return when the control pin is set
back HIGH.
Additionally, PWR_DWN and OE can be configured to occur
asynchronously or synchronously with respect to CLKOUT. In
asynchronous mode, PWR_DWN or OE disables CLKOUT
immediately (allowing for logic delays), without respect to the
current state of CLKOUT. Synchronous mode prevents output
glitches by waiting for the next falling edge of CLKOUT after
PWR_DWN, or OE becomes asserted. In either asynchronous
or synchronous setting, the output is always enabled
synchronously by waiting for the next falling edge of CLKOUT.
PROM Configuration Block
Table 1. PROM Adjustable Features
PROM Adjustable Features
Adjust
Freq.
Feedback counter value (P)
Reference counter value (Q)
Output divider selection
Duty cycle levels (TTL or CMOS)
Power management mode (OE or PWR_DWN)
Power management timing (synchronous or asynchronous)
Table 2. Device Functionality: Output Frequencies
Symbol
Fo
Description
Output frequency
Condition
V
DD
= 4.5 V–5.5 V
V
DD
= 3.0 V–3.6 V
Min
0.39
0.39
Max
133
100
Unit
MHz
MHz
Note
2. When using CyClocks, note that the PLL frequency range is from 50 MHz to 250 MHz for 5 V V
DD
supply, and 50 MHz to 180 MHz for 3 V V
DD
supply. The output
frequency is determined by the selected output divider.
Document Number: 38-07210 Rev. *J
Page 4 of 20
CY2077
Absolute Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Supply voltage ................................................ –0.5 to +7.0 V
Input voltage ........................................ –0.5 V to V
DD
+0.5 V
Storage temperature (non-condensing) ..... –55°C to +150°C
Junction temperature ................................................. 150°C
Static discharge voltage
(per MIL-STD-883, method 3015) ......................... > 2000 V
Operating Conditions
For Commercial Temperature Device
Parameter
V
DD
T
A
C
TTL
Supply voltage
Operating temperature, ambient
Max. capacitive load on outputs for TTL levels
V
DD
= 4.5 V–5.5 V, output frequency = 1 MHz–40 MHz
V
DD
= 4.5 V–5.5 V, output frequency = 40 MHz–125 MHz
V
DD
= 4.5 V–5.5 V, output frequency = 125 MHz–133 MHz
C
CMOS
Max. capacitive load on outputs for CMOS levels
V
DD
= 4.5 V–5.5 V, output frequency = 1 MHz–40 MHz
V
DD
= 4.5 V–5.5 V, output frequency = 40 MHz–125 MHz
V
DD
= 4.5 V–5.5 V, output frequency = 125 MHz–133 MHz
V
DD
= 3.0 V–3.6 V, output frequency = 1 MHz–40 MHz
V
DD
= 3.0 V–3.6 V, output frequency = 40 MHz–100 MHz
X
REF
t
PU
Reference frequency, input crystal with C
load
= 10 pF
Reference frequency, external clock source
Power-up time for all VDD’s to reach minimum specified voltage (power ramps must
be monotonic)
Description
Min
3.0
0
–
–
–
–
–
–
–
–
10
1
0.05
Max
5.5
+70
50
25
15
50
25
15
30
15
30
75
50
Unit
V
°C
pF
pF
pF
pF
pF
pF
pF
pF
MHz
MHz
ms
Document Number: 38-07210 Rev. *J
Page 5 of 20
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