LVPECL Frequency-Programmable VCXO
IDT8N3SV75
DATASHEET
General Description
The IDT8N3SV75 is a LVPECL Frequency-Programmable VCXO
with very flexible frequency and pull-range programming capabilities.
The device uses IDT’s fourth generation FemtoClock
®
NG
technology for an optimum of high clock frequency and low phase
noise performance. The device accepts 2.5V or 3.3V supply and is
packaged in a small, lead-free (RoHS 6) 6-lead ceramic 5mm x 7mm
x 1.55mm package.
The device can be factory-programmed to any frequency in the
range of 15.476MHz to 866.67MHz and from 975MHz to 1,300MHz
to the very high degree of frequency precision of 218Hz or better.
The extended temperature range supports wireless infrastructure,
telecommunication and networking end equipment requirements.
Features
•
•
•
•
•
•
•
•
•
•
•
Fourth generation FemtoClock
®
NG technology
Programmable clock output frequency from 15.476MHz to
866.67MHz and from 975MHz to 1,300MHz
Frequency programming resolution is 218Hz and better
Factory-programmable VCXO pull range and control voltage
polarity
Absolute pull range (APR) programmable from typical ±4.5 to
±754.5ppm
One 2.5V/3.3V LVPECL clock output
Output enable control input, LVCMOS/LVTTL compatible
RMS phase jitter @ 156.25MHz (12kHz - 20MHz): 0.5ps (typical),
2.5V or 3.3V supply voltage
-40°C to 85°C ambient operating temperature
Lead-free (RoHS 6) 6-lead ceramic 5mm x 7mm x 1.55mm
package
Block Diagram
Pin Assignment
VC
1
2
3
6
5
4
V
CC
nQ
Q
OE
OSC
114.285 MHz
2
÷P
PFD
&
LPF
FemtoClock® NG
VCO
1950-2600MHz
÷N
Q
nQ
V
EE
÷MINT,
MFRAC
7
VC
A/D
IDT8N3SV75
6-lead ceramic 5mm x 7mm x 1.55mm
package body
CD Package
Top View
7
25
Configuration Register (ROM)
(Frequency, Pull-range, Polarity)
OE
Pullup
IDT8N3SV75CCD REVISION A NOVEMBER 19, 2013
1
©2013 Integrated Device Technology, Inc.
IDT8N3SV75 Data Sheet
LVPECL-FREQUENCY PROGRAMMABLE VCXO
Pin Description and Characteristic Tables
Table 1. Pin Descriptions
Number
1
2
3
4, 5
6
Name
VC
OE
V
EE
Q, nQ
V
CC
Input
Input
Power
Output
Power
Pullup
Type
Description
VCXO Control Voltage input.
Output enable pin. See Table 3A for function. LVCMOS/LVTTL interface
levels.
Negative power supply.
Differential clock output. LVPECL interface levels.
Positive power supply.
NOTE:
Pullup
refers to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLUP
Parameter
Input Capacitance
Input Pullup Resistor
OE
VC
Test Conditions
Minimum
Typical
5.5
10
50
Maximum
Units
pF
pF
k
Function Tables
Table 3A. OE Configuration
Input
OE
0
1 (default)
Output Enable
Outputs Q, nQ are in high-impedance state.
Outputs are enabled.
Table 3B. Output Frequency Range
15.476MHz to 866.67MHz
975MHz to 1,300MHz
NOTE: Supported output frequency range. The output frequency can be programmed to any frequency in this range and to a precision of
218Hz or better.
IDT8N3SV75CCD REVISION A NOVEMBER 19, 2013
2
©2013 Integrated Device Technology, Inc.
IDT8N3SV75 Data Sheet
LVPECL-FREQUENCY PROGRAMMABLE VCXO
Principles of Operation
The block diagram consists of the internal 3rd overtone crystal and
oscillator which provide the reference clock f
XTAL
of 114.285MHz.
The PLL includes the FemtoClock® NG VCO along with the
Pre-divider (P), the feedback divider (M) and the post divider (N). The
P, M,
and
N
dividers determine the output frequency based on the
f
XTAL
reference. The feedback divider is fractional supporting a huge
number of output frequencies. Internal registers are used to hold up
the factory pre-set configuration setting. The
P, M,
and
N
frequency
configurations support an output frequency range 15.476MHz to
866.67MHz and 975MHz to 1,300MHz.
The devices use the fractional feedback divider with a delta-sigma
modulator for noise shaping and robust frequency synthesis
capability. The relatively high reference frequency minimizes phase
noise generated by frequency multiplication and allows more efficient
shaping of noise by the delta-sigma modulator. The output frequency
is determined by the 2-bit pre-divider (P), the feedback divider (M)
and the 7-bit post divider (N). The feedback divider (M) consists of
both a 7-bit integer portion (MINT) and an 18-bit fractional portion
(MFRAC) and provides the means for high-resolution frequency
generation. The output frequency f
OUT
is calculated by:
1
MFRAC
+ 0.5
f OUT
=
f XTAL
------------
MINT
+
------------------------------------
-
-
P
N
18
2
Frequency Configuration
An order code is assigned to each frequency configuration and the
VCXO pull-range programmed by the factory (default frequencies).
For more information on the available default frequencies and order
codes, please see the Ordering Information Section in this document.
For available order codes, see the
FemtoClock NG Ceramic-Package
XO and VCXO Ordering Product Information
document.
For more information on programming capabilities of the device for
custom frequency and pull-range configurations, see the
FemtoClock
NG Ceramic 5x7 Module Programming Guide.
IDT8N3SV75CCD REVISION A NOVEMBER 19, 2013
3
©2013 Integrated Device Technology, Inc.
IDT8N3SV75 Data Sheet
LVPECL-FREQUENCY PROGRAMMABLE VCXO
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. These ratings are stress
specifications only. Functional operation of the product at these conditions or any conditions beyond those listed in the
DC Characteristics or
AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability
.
Item
Supply Voltage, V
CC
Inputs, V
I
Outputs, I
O
(LVPECL)
Continuous Current
Surge Current
Package Thermal Impedance,
JA
Storage Temperature, T
STG
Rating
3.63V
-0.5V to V
CC
+ 0.5V
50mA
100mA
49.4C/W (0 mps)
-65C to 150C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics,
V
CC
= 3.3V ± 5%, V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
V
CC
I
EE
Parameter
Power Supply Voltage
Power Supply Current
Test Conditions
Minimum
3.135
Typical
3.3
130
Maximum
3.465
160
Units
V
mA
Table 4B. Power Supply DC Characteristics,
V
CC
= 2.5V ± 5%, V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
V
CC
I
EE
Parameter
Power Supply Voltage
Power Supply Current
Test Conditions
Minimum
2.375
Typical
2.5
120
Maximum
2.625
155
Units
V
mA
Table 4C. LVPECL DC Characteristics,
V
CC
= 3.3V ± 5%, V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
V
OH
V
OL
V
SWING
Parameter
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Peak-to-Peak Output Voltage
Swing
Test Conditions
Minimum
V
CC
– 1.4
V
CC
– 2.0
0.6
Typical
Maximum
V
CC
– 0.8
V
CC
– 1.7
1.0
Units
V
V
V
NOTE 1: Outputs terminated with 50
to V
CC
– 2V.
Table 4D. LVPECL DC Characteristics,
V
CC
= 2.5V ± 5%, V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
V
OH
V
OL
V
SWING
Parameter
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Peak-to-Peak Output Voltage
Swing
Test Conditions
Minimum
V
CC
– 1.4
V
CC
– 2.0
0.4
Typical
Maximum
V
CC
– 0.8
V
CC
– 1.5
1.0
Units
V
V
V
NOTE 1: Outputs terminated with 50 to V
CC
– 2V.
IDT8N3SV75CCD REVISION A NOVEMBER 19, 2013
4
©2013 Integrated Device Technology, Inc.
IDT8N3SV75 Data Sheet
LVPECL-FREQUENCY PROGRAMMABLE VCXO
Table 4E. LVCMOS/LVTTL DC Characteristic,
V
CC
= 3.3V ± 5% or 2.5V ± 5%, V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
V
IH
V
IL
I
IH
I
IL
Parameter
Input High Voltage
Test Conditions
V
CC
= 3.3V
V
CC
= 2.5V
V
CC
= V
IN
= 3.465V
V
CC
= V
IN
= 2.5V
OE
OE
V
CC
= V
IN
= 3.465V or 2.625V
V
CC
= 3.465V or 2.625V, V
IN
= 0V
-150
Minimum
2
1.7
-0.3
-0.3
Typical
Maximum
V
CC
+ 0.3
V
CC
+ 0.3
0.8
0.7
5
Units
V
V
V
V
µA
µA
Input Low Voltage
Input High Current
Input Low Current
IDT8N3SV75CCD REVISION A NOVEMBER 19, 2013
5
©2013 Integrated Device Technology, Inc.
FPGA/CPLD
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
