GS71116TP/J/U
SOJ, TSOP, FP-BGA
Commercial Temp
Industrial Temp
Features
• Fast access time: 10, 12, 15ns
• CMOS low power operation: 100/85/70 mA at min. cycle time.
• Single 3.3V ± 0.3V power supply
• All inputs and outputs are TTL compatible
• Byte control
• Fully static operation
• Industrial Temperature Option: -40° to 85°C
• Package line up
J: 400mil, 44 pin SOJ package
TP: 400mil, 44 pin TSOP Type II package
U: 6 mm x 8 mm Fine Pitch Ball Grid Array package
64K x 16
1Mb Asynchronous SRAM
SOJ 64K x 16 Pin Configuration
A
4
A
3
A
2
A
1
A
0
CE
DQ
1
DQ
2
DQ
3
DQ
4
V
DD
V
SS
DQ
5
DQ6
DQ7
DQ
8
WE
A
15
A
14
A
13
A
12
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
10, 12, 15ns
3.3V V
DD
Center V
DD
& V
SS
Top view
44 pin
SOJ
Description
The GS71116 is a high speed CMOS static RAM organized as
65,536-words by 16-bits. Static design eliminates the need for exter-
nal clocks or timing strobes. Operating on a single 3.3V power supply
and all inputs and outputs are TTL compatible. The GS71116 is avail-
able in a 6x8 mm Fine Pitch BGA package as well as in 400 mil SOJ
and 400 mil TSOP Type-II packages.
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A
5
A
6
A
7
OE
UB
LB
DQ
16
DQ
15
DQ
14
DQ
13
V
SS
V
DD
DQ
12
DQ
11
DQ
10
DQ
9
NC
A
8
A
9
A
10
A
11
NC
Pin Descriptions
Symbol
A
0
to A
15
DQ
1
to DQ
16
CE
LB
UB
WE
OE
V
DD
V
SS
NC
Description
Address input
Data input/output
Chip enable input
Lower byte enable input
(DQ1 to DQ8)
Upper byte enable input
(DQ9 to DQ16)
Write enable input
Output enable input
+3.3V power supply
Ground
No connect
Fine Pitch BGA 64K x 16 Bump Configuration
1
2
3
4
5
6
A
B
C
D
E
F
G
H
LB
DQ
16
OE
UB
A
0
A
3
A
5
NC
NC
A
8
A
10
A
13
A
1
A
4
A
6
A
7
NC
A
9
A
11
A
14
A
2
CE
DQ
2
DQ
4
DQ
5
DQ
7
WE
A
15
NC
DQ
1
DQ
3
V
DD
V
SS
DQ
6
DQ
8
NC
DQ
14
DQ
15
V
SS
V
DD
DQ
13
DQ
12
DQ
11
DQ
10
DQ
9
NC
NC
A
12
6mm x 8mm, 0.75mm Bump Pitch
Top View
Rev: 1.06 6/2000
1/15
© 1999, Giga Semiconductor, Inc.
M
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS71116TP/J/U
TSOP-II 64K x 16 Pin Configuration
A
4
A
3
A
2
A
1
A
0
CE
DQ
1
DQ
2
DQ
3
DQ
4
V
DD
V
SS
DQ
5
DQ
6
DQ
7
DQ
8
WE
A
15
A14
A
13
A
12
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A
5
A
6
A
7
OE
UB
LB
DQ
16
DQ
15
DQ
14
DQ
13
V
SS
V
DD
DQ
12
DQ
11
DQ
10
DQ
9
NC
A
8
A
9
A
10
A
11
NC
Top view
44 pin
TSOP II
Block Diagram
A
0
Address
Input
Buffer
Row
Decoder
Memory Array
A
15
CE
WE
Control
OE
UB
_____
LB
_____
Column
Decoder
I/O Buffer
DQ
1
DQ
16
Rev: 1.06 6/2000
2/15
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS71116TP/J/U
Truth Table
CE
H
OE
X
WE
X
LB
X
L
UB
X
L
H
L
L
H
L
X
H
DQ
1
to DQ
8
Not Selected
Read
Read
High Z
Write
Write
Not Write, High Z
High Z
High Z
DQ
9
to DQ
16
Not Selected
Read
High Z
Read
Write
Not Write, High Z
Write
High Z
High Z
V
DD
Current
ISB
1
, ISB
2
L
L
H
L
H
L
L
X
L
L
H
I
DD
L
L
H
X
H
X
X
H
Note: X: “H” or “L”
Absolute Maximum Ratings
Parameter
Supply Voltage
Input Voltage
Output Voltage
Allowable power dissipation
Storage temperature
Symbol
V
DD
V
IN
V
OUT
PD
T
STG
Rating
-0.5 to +4.6
-0.5 to V
DD
+0.5
(
≤
4.6V max.)
-0.5 to V
DD
+0.5
(
≤
4.6V max.)
0.7
-55 to 150
Unit
V
V
V
W
o
C
Note:
Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation shall be restricted to Recommended
Operating Conditions. Exposure to higher than recommended voltages for extended periods of time could affect device reliability.
Rev: 1.06 6/2000
3/15
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS71116TP/J/U
Recommended Operating Conditions
Parameter
Supply Voltage for -12/15
Supply Voltage for -10
Input High Voltage
Input Low Voltage
Ambient Temperature,
Commercial Range
Ambient Temperature,
Industrial Range
Symbol
V
DD
V
DD
V
IH
V
IL
T
Ac
T
A
I
Min
3.0
3.135
2.0
-0.3
0
-40
Typ
3.3
3.3
-
-
-
-
Max
3.6
3.6
V
DD
+0.3
0.8
70
85
Unit
V
V
V
V
o
C
C
o
Note:
1. Input overshoot voltage should be less than V
DD
+2V and not exceed 20ns.
2. Input undershoot voltage should be greater than -2V and not exceed 20ns.
Capacitance
Parameter
Input Capacitance
Output Capacitance
Symbol
C
IN
C
OUT
Test Condition
V
IN
=0V
V
OUT
=0V
Max
5
7
Unit
pF
pF
Notes:
1. Tested at T
A
=25°C, f=1MHz
2. These parameters are sampled and are not 100% tested
DC I/O Pin Characteristics
Parameter
Input Leakage
Current
Output Leakage
Current
Output High Voltage
Output Low Voltage
Symbol
I
IL
I
LO
V
OH
V
OL
Test Conditions
V
IN
= 0 to V
DD
Output High Z
V
OUT
= 0 to V
DD
I
OH
= - 4mA
I
LO
= + 4mA
Min
-1uA
-1uA
2.4
Max
1uA
1uA
0.4V
Rev: 1.06 6/2000
4/15
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS71116TP/J/U
Power Supply Currents
0 to 70°C
Parameter
Symbol
Test Conditions
10ns
Operating
Supply
Current
CE
≤
V
IL
All other inputs
≥
V
IH
or
≤
V
IL
Min. cycle time
I
OUT
= 0 mA
CE
≥
V
IH
All other inputs
≥
V
IH
or
≤
V
IL
Min. cycle time
CE
≥
V
DD
- 0.2V
All other inputs
≥
V
DD
- 0.2V or
≤
0.2V
-40 to 85°C
15ns
10ns
12ns
15ns
12ns
I
DD
(max)
100mA
85mA
70mA
115mA
100mA
85mA
Standby
Current
I
SB1
(max)
45mA
40mA
35mA
50mA
45mA
40mA
Standby
Current
I
SB2
(max)
10mA
15mA
Rev: 1.06 6/2000
5/15
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
模拟电子
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
