GS1881, GS4881, GS4981
Monolithic Video Sync Separators
DATA SHEET
FEATURES
• noise tolerant odd/even flag, back porch and
horizontal sync pulse
• fast recovery from impulse noise
• excellent temperature stability
• 0.5 V to 4 Vpp input signal amplitude with 5 V
supply
• well-controlled clamp discharge current and
slicing level
• programmable horizontal scan rate (up to 130 kHz)
• composite, vertical, back porch, odd/even
(GS1881, GS4881), horizontal (GS4981) outputs
• predictable vertical output pulse width with
default trigger for non-standard video signals
• 5 V to 12 V supply voltage range
• pin compatible with LM1881 sync separator
SELECTION CHART
DESCRIPTION
The GS1881, GS4881 and GS4981 are general purpose sync
separators for use in a wide variety of video applications. The
devices extract the timing information from composite video
signals with scan rates from 15 to 130 kHz.
The GS1881 is a drop-in replacement for the industry standard
LM1881 with much improved performance. The device
generates composite sync, vertical sync, back porch and
odd/even field signals. The GS4881 is identical to the GS1881
but features a noise immune back porch pulse which maintains
a constant H rate during the vertical interval. The GS4981 is
identical to the GS4881, except that it provides horizontal sync
in place of the odd/even output.
All three devices feature a self-adjusting windowing circuit for
noise immunity, which synchronizes to H rate. This
windowing c i r c u i t d e t e r m i n e s t h e o d d o r e v e n f i e l d
in the GS1881 and GS4881, gates the back porch pulse in
the GS4881 and GS4981, and generates the horizontal sync
output in the GS4981.
The devices feature an improved input stage which ensures
that the input signal is sliced at a predictable point due to
well-controlled input clamp discharge current and sync
slicing level. A missing pulse detector enables the devices to
recover quickly from impulse noise disturbances by temporarily
increasing the clamp discharge current by roughly ten times.
The input stage will operate with signals from 0.5 to 4 volts
peak to peak with a 5 volt supply.
The GS1881, GS4881 and GS4981 also feature a predictable
vertical output pulse width with a default trigger for non-standard
video signals. All three are available in commercial and
industrial temperature ranges and are packaged in both DIP
and SOIC.
APPLICATION
Direct LM1881 Replacement
with Improved Performance
New Applications
Substitution for LM1881
New Applications Requiring
Horizontal Sync Output
CHOOSE DEVICE:
GS1881
GS4881
GS4981
PIN CONNECTIONS
GS1881, GS4881
COMPOSITE
SYNC OUT
COMPOSITE
VIDEO IN
VERTICAL
SYNC OUT
GROUND
1
2
3
4
8
7
6
5
V
COMPOSITE
SYNC OUT
COMPOSITE
VIDEO IN
VERTICAL
SYNC OUT
GROUND
1
2
3
4
GS4981
8
7
6
5
V
cc
cc
ODD/EVEN
R
SET
BACK PORCH
HORIZONTAL
R
SET
BACK PORCH
8 PIN DIP
8 PIN SOIC
Patent No. 5,432,559
Revision Date: October 1995
8 PIN DIP
8 PIN SOIC
Document No. 520 - 23 - 03
GENNUM CORPORATION P.O. Box 489, Stn A, Burlington, Ontario, Canada L7R 3Y3 tel. (905) 632-2996 fax: (905) 632-2055
Japan Branch: A-302 Miyamae Village, 2-10-42 Miyamae, Suginami-ku, Tokyo 168, Japan
tel. (03) 3247-8838
fax (03) 3247-8839
GS1881 ELECTRICAL CHARACTERISTICS
PARAMETER
Supply Voltage
Supply Current
(V
CC
= 5 V, R
SET
= 680 kΩ, T
A
= 25° C, unless otherwise specified)
CONDITIONS
MIN
4.5
TYP
5
4.6
5.0
MAX
13.2
6.5
7.0
UNITS
V
mA
mA
Outputs at Logic 1
V
CC
= 5 V
V
CC
= 12 V
-
-
Video Input (Pin 2)
(a) Signal Level
(b) Clamp Current
V
CC
= 5 V
Charge
Discharge - normal
- Nosync flag raised
(c) Delay to raising of Nosync flag Video input held high
(d) Sync Tip Clamp Voltage
Sync Slice Level
R
SET
Pin Reference Voltage (Pin 6)
Composite Sync Out (Pin 1)
Delay from Video
Back Porch Pulse Out (Pin 5)
(a) Delay from Rising
Edge of Sync
(b) Pulse Width
Vertical Sync Out (Pin 3)
(a) Pulse Width
(b) Default Starting Time
Horizontal Scan Rate
Logic Outputs
(a) V
OH
I
OH
= 40
µA
I
OH
= 1.6 mA
(b) V
OL
Note 1: When placing the R
SET
0.5
500
9
65
64
-
-
650
11
95
95
1.55
77
1.24
60
4
850
13
115
130
-
84
1.34
80
Vp-p
µA
µA
µA
µs
V
mV
V
ns
Relative to sync tip clamp voltage
See Note 1
See Note 2
C
L
= 15p
C
L
= 15p
70
1.14
40
400
2.0
500
2.5
650
3.2
ns
µs
µs
µs
kHz
Serrations during vertical interval
No serrations during the vertical interval
Modified R
SET
V
CC
= 5 V
V
CC
= 12 V
V
CC
= 5 V
V
CC
= 12 V
I
OL
= -1.6 mA
197.7
48
15
197.7
65
-
197.7
82
130
4.2
11.2
2.4
9.4
-
4.6
11.6
3.4
10.4
0.3
-
-
-
-
0.6
V
V
V
V
V
resistor and the 0.1µF decoupling capacitor careful attention should be made to ensure that they are as close
as possible to pin 6. Care should also be taken to avoid parasitic capacitive coupling from any output pin (pins 1, 3, 5 and 7) to pin 6.
Note 2: Measured from slicing point of input falling edge to 50% point of composite sync falling edge.
ORDERING INFORMATION
Part Number
GS1881 - CDA
GS1881 - CKA
GS1881 - CTA
GS1881 - IDA
GS1881 - IKA
GS1881 - ITA
Package Type
8 PDIP
8 SOIC
8 TAPE
8 PDIP
8 SOIC
8 TAPE
Temperature Range
0° to 70° C
0° to 70° C
0° to 70° C
-25° to 85° C
CAUTION
-25° to 85° C
-25° to 85° C
ELECTROSTATIC
SENSITIVE DEVICES
DO NOT OPEN PACKAGES OR HANDLE
EXCEPT AT A STATIC-FREE WORKSTATION
520 - 23 - 03
2
GS4881 ELECTRICAL CHARACTERISTICS
PARAMETER
Supply Voltage
Supply Current
(V
CC
= 5 V, R
SET
= 680 kΩ, T
A
= 25° C, unless otherwise specified)
CONDITIONS
MIN
4.5
TYP
5
4.6
5.0
MAX
13.2
6.5
7.0
UNITS
V
mA
mA
Outputs at Logic 1
V
CC
= 5 V
V
CC
= 12 V
-
-
Video Input (Pin 2)
(a) Signal Level
(b) Clamp Current
V
CC
= 5 V
Charge
Discharge - normal
- Nosync flag raised
(c) Delay to raising of Nosync flag Video input held high
(d) Sync Tip Clamp Voltage
Sync Slice Level
R
SET
Pin Reference Voltage (Pin 6)
Composite Sync Out (Pin 1)
Delay from Video
Back Porch Pulse Out (Pin 5)
(a) Delay from Rising
Edge of Sync
(b) Pulse Width
(c) Occurence Rate
Vertical Sync Out (Pin 3)
(a) Pulse Width
(b) Default Starting Time
Horizontal Scan Rate
Logic Outputs
(a) V
OH
I
OH
= 40
µA
I
OH
= 1.6 mA
(b) V
OL
I
OL
= -1.6 mA
V
CC
= 5 V
V
CC
= 12 V
V
CC
= 5 V
V
CC
= 12 V
4.2
11.2
2.4
9.4
-
4.6
11.6
3.4
10.4
0.3
-
-
-
-
0.6
V
V
V
V
V
Serrations during vertical interval
No serrations during the vertical interval
Modified R
SET
197.7
48
15
197.7
65
-
197.7
82
130
µs
µs
kHz
400
2.0
H
500
2.5
H
650
3.2
H
ns
µs
Relative to sync tip clamp voltage
See Note 1
See Note 2
C
L
= 15p
C
L
= 15p
0.5
500
9
65
64
-
70
1.14
40
-
650
11
95
95
1.55
77
1.24
60
4
850
13
115
130
-
84
1.34
80
Vp-p
µA
µA
µA
µs
V
mV
V
ns
Note 1: When placing the R
SET
resistor and the 0.1µF decoupling capacitor careful attention should be made to ensure that they are as close
as possible to pin 6. Care should also be taken to avoid parasitic capacitive coupling from any output pin (pins 1, 3, 5 and 7) to pin 6.
Note 2: Measured from slicing point of input falling edge to 50% point of composite sync falling edge.
ORDERING INFORMATION
Part Number
GS4881 - CDA
GS4881 - CKA
GS4881 - CTA
GS4881 - IDA
GS4881 - IKA
GS4881 - ITA
Package Type
8 PDIP
8 SOIC
8 TAPE
8 PDIP
8 SOIC
8 TAPE
Temperature Range
0° to 70° C
0° to 70° C
0° to 70° C
-25° to 85° C
-25° to 85° C
-25° to 85° C
3
520 - 23 - 03
GS4981 ELECTRICAL CHARACTERISTICS
PARAMETER
Supply Voltage
Supply Current
(V
CC
= 5 V, R
SET
= 680 kΩ, T
A
= 25° C, unless otherwise specified)
CONDITIONS
MIN
4.5
TYP
5
4.6
5.0
MAX
13.2
6.5
7.0
UNITS
V
mA
mA
Outputs at Logic 1
V
CC
= 5 V
V
CC
= 12 V
-
-
Video Input (Pin 2)
(a) Signal Level
(b) Clamp Current
V
CC
= 5 V
Charge
Discharge - normal
- Nosync flag raised
(c) Delay to raising of Nosync flag Video input held high
(d) Sync Tip Clamp Voltage
Sync Slice Level
R
SET
Pin Reference Voltage (Pin 6)
Composite Sync Out (Pin 1)
Delay from Video
Back Porch Pulse Out (Pin 5)
(a) Delay from Rising
Edge of Sync
(b) Pulse Width
(c) Occurence Rate
Vertical Sync Out (Pin 3)
(a) Pulse Width
(b) Default Starting Time
Horizontal Sync Out (Pin 7)
(a) Delay from Video
(b) Pulse Width
Horizontal Scan Rate
Logic Outputs
(a) V
OH
I
OH
= 40
µA
I
OH
= 1.6 mA
Note 3
(b) V
OL
I
OL
= -1.6 mA
V
CC
= 5 V
V
CC
= 12 V
V
CC
= 5 V
V
CC
= 12 V
4.2
11.2
2.4
9.4
-
4.6
11.6
3.4
10.4
0.3
-
-
-
-
0.6
V
V
V
V
V
Modified R
SET
Serrations during vertical interval
No serrations during the vertical interval
C
L
= 15p
90
5.0
15
190
7.0
-
290
9.0
130
ns
µs
kHz
197.7
48
197.7
65
197.7
82
µs
µs
400
2.0
H
500
2.5
H
650
3.2
H
ns
µs
Relative to sync tip clamp voltage
See Note 1
See Note 2
C
L
= 15p
C
L
= 15p
0.5
500
9
65
64
-
70
1.14
40
-
650
11
95
95
1.55
77
1.24
60
4
850
13
115
130
-
84
1.34
80
Vp-p
µA
µA
µA
µs
V
mV
V
ns
Note 1: When placing the R
SET
resistor and the 0.1µF decoupling capacitor careful attention should be made to ensure that they are as close
as possible to pin 6. Care should also be taken to avoid parasitic capacitive coupling from any output pin (pins 1, 3, 5 and 7) to pin 6.
Note 2: Measured from slicing point of input falling edge to 50% point of composite sync falling edge.
Note 3: Applies only to composite sync, vertical sync, and back porch outputs. Horizontal sync has a passive 10 kΩ pull-up to V
CC
.
ORDERING INFORMATION
Part Number
GS4981 - CDA
GS4981 - CKA
GS4981 - CTA
GS4981 - IDA
GS4981 - IKA
GS4981 - ITA
520 - 23 - 03
Package Type
8 PDIP
8 SOIC
8 TAPE
8 PDIP
8 SOIC
8 TAPE
Temperature Range
0° to 70° C
0° to 70° C
0° to 70° C
-25° to 85° C
-25° to 85° C
-25° to 85° C
4
TYPICAL PERFORMANCE CHARACTERISTICS
(V
S
= 5V, T
A
= 25° C unless otherwise shown)
700
600
500
70
VERTICAL DEFAULT TIME (µs)
15
35
55
75
95
115
135
60
50
40
30
20
10
0
0
100
200
300
400
500
600
700
R
SET
(kΩ)
400
300
200
100
0
SCAN RATE (kHz)
R
SET
(kΩ)
Fig. 1 R
SET
vs Scan Rate
Fig. 2 Vertical Sync Default Starting Time
vs R
SET
700
600
3000
BACK PORCH DELAY (ns)
2500
500
400
300
200
100
0
BACK PORCH WIDTH (ns)
2000
1500
1000
500
0
100
200
300
400
500
600
700
0
0
100
200
300
400
500
600
700
R
SET
(kΩ)
R
SET
(kΩ)
Fig. 3 Back Porch Delay vs R
SET
Fig. 4 Back Porch Width vs R
SET
8000
7000
110
100
HORIZONTAL WIDTH (µs)
6000
5000
4000
3000
2000
1000
0
0
100
200
300
400
500
600
700
NOSYNC DELAY TIME (µs)
90
80
70
60
50
40
30
20
10
0
0
100
200
300
400
500
600
700
R
SET
(kΩ)
R
SET
(kΩ)
Fig. 5 Horizontal Width vs R
SET
Fig. 6 Nosync Delay Time vs R
SET
5
520 - 23 - 03
ARM技术
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
