MM74HCT573 • MM74HCT574 Octal D-Type Latch • 3-STATE Octal D-Type Flip-Flop
February 1990
Revised May 2005
MM74HCT573 • MM74HCT574
Octal D-Type Latch • 3-STATE Octal D-Type Flip-Flop
General Description
The
MM74HCT573
octal
D-type
latches
and
MM74HCT574 octal D-type flip-flop advanced silicon-gate
CMOS technology, which provides the inherent benefits of
low power consumption and wide power supply range, but
are LS-TTL input and output characteristic and pin-out
compatible. The 3-STATE outputs are capable of driving 15
LS-TTL loads. All inputs are protected from damage due to
static discharge by internal diodes to V
CC
and ground.
When the MM74HCT573 Latch Enable input is HIGH, the
Q outputs will follow the D inputs. When the Latch Enable
goes LOW, data at the D inputs will be retained at the out-
puts until Latch Enable returns HIGH again. When a high
logic level is applied to the Output Control input, all outputs
go to a high impedance state, regardless of what signals
are present at the other inputs and the state of the storage
elements.
The MM74HCT574 are positive edge triggered flip-flops.
Data at the D inputs, meeting the setup and hold time
requirements, are transferred to the Q outputs on positive
going transitions of the Clock (CK) input. When a high logic
level is applied to the Output Control (OC) input, all outputs
go to a high impedance state, regardless of what signals
are present at the other inputs and the state of the storage
elements.
The MM74HCT devices are intended to interface between
TTL and NMOS components and standard CMOS devices.
These parts are also plug in replacements for LS-TTL
devices and can be used to reduce power consumption in
existing designs.
Features
s
TTL input characteristic compatible
s
Typical propagation delay: 18 ns
s
Low input current: 1
P
A maximum
s
Low quiescent current: 80
P
A maximum
s
Compatible with bus-oriented systems
s
Output drive capability: 15 LS-TTL loads
Ordering Codes:
Order Number
MM74HCT573WM
MM74HCT573SJ
MM74HCT573MTC
MM74HCT573N
MM74HCT574WM
MM74HCT574SJ
MM74HCT574MTC
MM74HCT574N
Package Number
M20B
M20D
MTC20
N20A
M20B
M20D
MTC20
N20A
Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
© 2005 Fairchild Semiconductor Corporation
DS010627
www.fairchildsemi.com
MM74HCT573 • MM74HCT574
Connection Diagrams
Truth Tables
MM74HCT573
Output
Control
L
L
L
H
LE
H
H
L
X
Data
H
L
X
X
Output
H
L
Q
0
Z
H HIGH Level
L LOW Level
Q
0
Level of output before steady-state input conditions were established.
Z High Impedance State
Top View
MM74HCT573
MM74HCT574
Output
Control
L
L
L
H
H
L
Q
0
X
Z
LE
Data
H
L
X
X
Output
H
L
Q
0
Z
n
n
L
X
n
HIGH Level
LOW Level
Level of output before steady-state input conditions were established.
Don’t Care
High Impedance State
Transition from LOW-to-HIGH
Top View
MM74HCT574
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2
MM74HCT573 • MM74HCT574
Absolute Maximum Ratings
(Note 1)
(Note 2)
Supply Voltage (V
CC
)
DC Input Voltage (V
IN
)
DC Output Voltage (V
OUT
)
Clamp Diode Current (I
IK
, I
OK
)
DC Output Current, per pin (I
OUT
)
DC V
CC
or GND Current, per pin (I
CC
)
Storage Temperature Range (T
STG
)
Power Dissipation (P
D
)
(Note 3)
S. O. Package only
Lead Temperature (T
L
)
(Soldering 10 seconds)
260
q
C
600 mW
500 mW
Recommended Operating
Conditions
Min
Supply Voltage (V
CC
)
DC Input or Output Voltage
(V
IN
, V
OUT
)
Operating Temperature Range (T
A
)
Input Rise or Fall Times
t
r
, t
f
500
ns
Note 1:
Absolute Maximum Ratings are those values beyond which dam-
age to the device may occur.
Note 2:
Unless otherwise specified all voltages are referenced to ground.
Note 3:
Power Dissipation temperature derating — plastic “N” package:
12 mW/
q
C from 65
q
C to 85
q
C.
0.5 to
7.0V
1.5 to V
CC
1.5V
0.5 to V
CC
0.5V
r
20 mA
r
35 mA
r
70 mA
65
q
C to
150
q
C
Max
5.5
V
CC
Units
V
V
4.5
0
40
85
q
C
DC Electrical Characteristics
V
CC
5V
r
10% (unless otherwise specified)
Parameter
Minimum HIGH Level
Input Voltage
V
IL
V
OH
Maximum LOW Level
Input Voltage
Minimum HIGH Level
Output Voltage
V
IN
|I
OUT
|
|I
OUT
|
|I
OUT
|
V
OL
Maximum LOW Level
Voltage
V
IN
|I
OUT
|
|I
OUT
|
|I
OUT
|
I
IN
I
OZ
Maximum Input
Current
Maximum 3-STATE
Output Leakage
Current
I
CC
Maximum Quiescent
Supply Current
V
IN
I
OUT
V
IN
V
CC
or GND
0
P
A
2.4V or 0.5V (Note 4)
1.5
1.8
2.0
mA
8.0
80
160
V
IN
V
OUT
Enable
V
IH
or V
IL
20
P
A
6.0 mA, V
CC
7.2 mA, V
CC
V
IH
or V
IL
20
P
A
6.0 mA, V
CC
7.2 mA, V
CC
V
CC
or GND,
V
CC
or GND
V
IH
or V
IL
4.5V
5.5V
0
0.2
0.2
0.1
0.26
0.26
0.1
0.33
0.33
0.1
0.4
0.4
V
4.5V
5.5V
V
CC
4.2
5.7
V
CC
0.1
3.98
4.98
V
CC
0.1
3.84
4.84
V
CC
0.1
3.7
4.7
V
0.8
0.8
0.8
V
Conditions
T
A
Typ
2.0
25
q
C
T
A
Symbol
V
IH
40 to 85
q
C T
A
55 to 125
q
C
Guaranteed Limits
2.0
2.0
Units
V
r
0.1
r
0.5
r
1.0
r
5.0
r
1.0
r
10
P
A
P
A
V
IH
or V
IL
P
A
Note 4:
Measured per pin. All others tied to V
CC
or ground.
3
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MM74HCT573 • MM74HCT574
AC Electrical Characteristics
MM74HCT573
V
CC
t
PHL
t
PLH
t
PHL
t
PLH
t
PZH
t
PZL
t
PHZ
t
PLZ
t
W
t
S
t
H
5.0V, t
r
t
f
6 ns, T
A
25
q
C (unless otherwise specified)
Parameter
Conditions
C
L
C
L
45 pF
45 pF
45 pF
1 k
:
5 pF
1 k
:
15
5
12
ns
ns
ns
14
23
ns
Typ
17
16
21
Guaranteed Limit
27
27
30
Units
ns
ns
ns
Symbol
Maximum Propagation Delay
Data to Output
Maximum Propagation Delay
Latch Enable to Output
Maximum Enable Propagation Delay C
L
Control to Output
R
L
Maximum Disable Propagation Delay C
L
Control to Output
R
L
Minimum Clock Pulse Width
Minimum Setup Time Data to Clock
Minimum Hold Time Clock to Data
AC Electrical Characteristics
MM74HCT573
V
CC
5.0V
Symbol
t
PHL
t
PLH
t
PHL
t
PLH
t
PZH
t
PZL
t
PHZ
t
PLZ
t
THL
t
TLH
t
W
t
S
t
H
C
IN
C
OUT
C
PD
r
10%, t
r
t
f
6 ns (unless otherwise specified)
Conditions
C
L
C
L
C
L
R
L
C
L
R
L
C
L
50 pF
50 pF
50 pF
1 k
:
50 pF
1 k
:
50 pF
6
12
15
15
20
6
15
10
20
18
24
8
18
10
20
ns
ns
ns
ns
pF
pF
pF
15
30
38
45
ns
T
A
Typ
18
17
22
30
30
30
25
q
T
A
Parameter
Maximum Propagation
Delay Data to Output
Maximum Propagation Delay
Latch Enable to Output
Maximum Enable Propagation
Delay Control to Output
Maximum Disable Propagation
Delay Control to Output
Maximum Output
Rise and Fall Time
Minimum Clock Pulse Width
Minimum Setup Time Data to Clock
Minimum Hold Time Clock to Data
Maximum Input Capacitance
Maximum Output Capacitance
Power Dissipation Capacitance
(Note 5)
OC
OC
40 to 85
q
C T
A
Guaranteed Limits
38
44
38
55 to 125
q
C
45
53
45
Units
ns
ns
ns
3
4
5
12
10
20
V
CC
GND
5
52
C
PD
V
CC
2 f
I
CC
V
CC
, and the no load dynamic current consumption,
Note 5:
C
PD
determines the no load dynamic power consumption, P
D
I
S
C
PD
V
CC
f
I
CC
.
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4
MM74HCT573 • MM74HCT574
AC Electrical Characteristics
V
CC
f
MAX
t
PHL
t
PLH
t
PZH
t
PZL
t
PHZ
t
PLZ
t
W
t
S
t
H
MM74HCT574
Conditions
Typ
60
17
19
14
Guaranteed Limit
33
27
28
25
15
12
5
Units
MHz
ns
ns
ns
ns
ns
ns
5.0V, t
r
t
f
6 ns, T
A
25
q
C
Parameter
Symbol
Maximum Clock Frequency
Maximum Propagation Delay
to Output
Maximum Enable Propagation Delay
Control to Output
Maximum Disable Propagation Delay
Control to Output
Minimum Clock Pulse Width
Minimum Setup Time Data to Clock
Minimum Hold Time Clock to Data
C
L
R
L
C
L
R
L
45 pF
1 k
:
45 pF
1 k
:
C
L
45 pF
AC Electrical Characteristics
MM74HCT574
V
CC
5.0V
r
10%, t
r
t
f
6 ns (unless otherwise specified)
Parameter
Conditions
T
A
Typ
25
q
C
33
C
L
C
L
R
L
C
L
R
L
C
L
50 pF
50 pF
1 k
:
50 pF
1 k
:
50 pF
6
12
15
6
12
5
10
20
OC
OC
V
CC
GND
2
Symbol
f
MAX
t
PHL
t
PLH
t
PZH
t
PZL
t
PHZ
t
PLZ
t
THL
t
TLH
t
W
t
S
t
H
C
IN
C
OUT
C
PD
T
A
40 to 85
q
C T
A
28
38
38
38
15
20
15
6
10
20
55 to 125
q
C
23
45
45
45
18
24
18
8
10
20
Units
MHz
ns
ns
ns
ns
ns
ns
ns
pF
pF
pF
Guaranteed Limits
30
30
30
Maximum Clock Frequency
Maximum Propagation Delay
Clock to Output
Maximum Enable Propagation
Delay Control to Output
Maximum Disable Propagation
Delay Control to Output
Maximum Output
Rise and Fall Time
Minimum Clock Pulse Width
Minimum Setup Time Data to Clock
Minimum Hold Time Clock to Data
Maximum Input Capacitance
Maximum Output Capacitance
Power Dissipation Capacitance
(Note 6)
5
58
22
15
18
1
Note 6:
C
PD
determines the no load power consumption, P
D
C
PD
V
CC
f
I
CC
V
CC
, and the no load dynamic current consumption, I
S
C
PD
V
CC
f
I
CC
.
5
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