CAT15002, CAT15004
Voltage Supervisor with
2-Kb and 4-Kb SPI Serial
CMOS EEPROM
Description
The CAT15002/04 (see table below) are memory and supervisory
solutions for microcontroller based systems. A CMOS serial
EEPROM memory and a system power supervisor with brown−out
protection are integrated together. Memory interface is via SPI bus
serial interface.
The CAT15002/04 provides a precision V
CC
sense circuit with two
reset output options: CMOS active low output or CMOS active high.
The RESET output is active whenever V
CC
is below the reset
threshold or falls below the reset threshold voltage.
The power supply monitor and reset circuit protect system
controllers during power up/down and against brownout conditions.
Seven reset threshold voltages support 5 V, 3.3 V, 3 V and 2.5 V
systems. If power supply voltages are out of tolerance reset signals
become active, preventing the system microcontroller, ASIC or
peripherals from operating. Reset signals become inactive typically
240 ms after the supply voltage exceeds the reset threshold level.
Features
♦
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SOIC−8
CASE 751BD
PIN CONFIGURATION
SOIC (W)
CS
SO
WP
V
SS
1
2
3
4
8
7
6
5
V
CC
RST/RST
SCK
SI
•
Precision Power Supply Voltage Monitor
•
•
•
•
•
•
•
•
•
5 V, 3.3 V, 3 V and 2.5 V Systems
♦
7 Threshold Voltage Options
Active High or Low Reset
♦
Valid Reset Guaranteed at V
CC
= 1 V
10 MHz SPI Compatible
16−Byte Page Write Buffer
Low Power CMOS Technology
1,000,000 Program/Erase Cycles
100 Year Data Retention
Industrial Temperature Range
RoHS−Compliant 8−Pin SOIC Package
These Devices are Pb−Free, Halogen Free/BFR Free
and are RoHS Compliant
PIN FUNCTION
Pin Name
CS
SO
WP
V
SS
SI
SCK
RST/RST
V
CC
Function
Chip Select
Serial Data Output
Write Protect
Ground
Serial Data Input
Serial Clock Input
Reset Output
Power Supply
MEMORY SIZE SELECTOR
Product
15002
15004
Memory Density
2−Kbit
4−Kbit
THRESHOLD SUFFIX SELECTOR
Nominal Threshold Voltage
4.63 V
4.38 V
4.00 V
3.08 V
2.93 V
2.63 V
2.32 V
Threshold Suffix
Designation
L
M
J
T
S
R
Z
ORDERING INFORMATION
For Ordering Information details, see page 11.
©
Semiconductor Components Industries, LLC, 2011
November, 2011
−
Rev. 3
1
Publication Order Number:
CAT15002/D
CAT15002, CAT15004
BLOCK DIAGRAM
V
CC
SO
SCK
SI
CS
WP
EEPROM
VOLTAGE
DETECTOR
RST or RST
V
SS
SPECIFICATIONS
Table 1. ABSOLUTE MAXIMUM RATINGS
Parameters
Storage Temperature
Voltage on Any Pin with Respect to Ground (Note 1)
Ratings
–65 to +150
−0.5
to +6.5
Units
°C
V
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. The DC input voltage on any pin should not be lower than
−0.5
V or higher than V
CC
+ 0.5 V. During transitions, the voltage on any pin may
undershoot to no less than
−1.5
V or overshoot to no more than V
CC
+ 1.5 V, for periods of less than 20 ns.
Table 2. RELIABILITY CHARACTERISTICS
(Note 2)
Symbol
NEND (Note 3)
TDR
Endurance
Data Retention
Parameter
Min
1,000,000
100
Units
Program/ Erase Cycles
Years
2. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
3. Page Mode, V
CC
= 5 V, 25°C
Table 3. D.C. OPERATING CHARACTERISTICS
V
CC
= +2.5 V to +5.5 V, unless otherwise specified.
Symbol
I
CC
I
SB
I
L
V
IL
V
IH
V
OL
V
OH
Parameter
Supply Current
Standby Current
Test Conditions
Read or Write at 10 MHz, SO open
V
CC
< 5.5 V; V
IN
= V
SS
or V
CC
, CS = V
CC
V
CC
< 3.6 V; V
IN
= V
SS
or V
CC
, CS = V
CC
I/O Pin Leakage
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
V
CC
≥
2.5 V, I
OL
= 3.0 mA
V
CC
≥
2.5 V, I
OH
=
−1.6
mA
V
CC
−
0.8
Pin at GND or V
CC
−0.5
0.7 V
CC
12
10
Min
Typ
Max
2
25
20
2
0.3 V
CC
V
CC
+ 0.5
0.4
mA
V
V
V
V
Units
mA
mA
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CAT15002, CAT15004
Table 4. A.C. CHARACTERISTICS (MEMORY)
(Note 1)
V
CC
= 2.5 V to 5.5 V, T
A
=
−40°C
to 85°C, unless otherwise specified.
Symbol
f
SCK
t
SU
t
H
t
WH
t
WL
t
LZ
t
RI
(Note 2)
t
FI
(Note 2)
t
HD
t
CD
t
V
t
HO
t
DIS
t
HZ
t
CS
t
CSS
t
CSH
t
WPS
t
WPH
t
WC
(Note 4)
t
PU
(Notes 2 & 3)
1.
2.
3.
4.
Clock Frequency
Data Setup Time
Data Hold Time
SCK High Time
SCK Low Time
HOLD to Output Low Z
Input Rise Time
Input Fall Time
HOLD Setup Time
HOLD Hold Time
Output Valid from Clock Low
Output Hold Time
Output Disable Time
HOLD to Output High Z
CS High Time
CS Setup Time
CS Hold Time
WP Setup Time
WP Hold Time
Write Cycle Time
Power−up to Ready Mode
15
15
15
10
10
5
1
0
20
25
0
10
40
Parameter
Min
DC
20
20
40
40
25
2
2
Max
10
Units
MHz
ns
ns
ns
ns
ns
ms
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ms
Test conditions according to “A.C. Test Conditions” table.
Tested initially and after a design or process change that affects this parameter.
t
PU
is the delay between the time V
CC
is stable and the device is ready to accept commands.
t
WC
is the time from the rising edge of CS after a valid write sequence to the end of the internal write cycle.
Table 5. A.C. TEST CONDITIONS
Parameter
Input Rise and Fall Times
Input Levels
Timing Reference Levels
Output Load
Test Conditions
≤10
ns
0.3 V
CC
to 0.7 V
CC
0.5 V
CC
Current Source: I
OL
max/ I
OH
max; C
L
= 50 pF
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CAT15002, CAT15004
Table 6. ELECTRICAL CHARACTERISTICS (SUPERVISORY FUNCTION)
V
CC
= Full range, T
A
=
−40°C
to +85°C unless otherwise noted. Typical values at T
A
= +25°C and V
CC
= 5 V for L/M/J versions,
V
CC
= 3.3 V for T/S versions, V
CC
= 3 V for R version and V
CC
= 2.5 V for Z version.
Symbol
V
TH
Parameter
Reset Threshold
Voltage
Threshold
L
T
A
= +25°C
T
A
=
−40°C
to +85°C
M
T
A
= +25°C
T
A
=
−40°C
to +85°C
J
T
A
= +25°C
T
A
=
−40°C
to +85°C
T
T
A
= +25°C
T
A
=
−40°C
to +85°C
S
T
A
= +25°C
T
A
=
−40°C
to +85°C
R
T
A
= +25°C
T
A
=
−40°C
to +85°C
Z
T
A
= +25°C
T
A
=
−40°C
to +85°C
Symbol
Parameter
Reset Threshold Tempco
t
RPD
t
PURST
V
OL
V
CC
to Reset Delay (Note 2)
Reset Active Timeout Period
RESET Output Voltage Low
(Push−pull, Active LOW,
CAT150xx9)
V
CC
= V
TH
to (V
TH
−100
mV)
T
A
=
−40°C
to +85°C
V
CC
= V
TH
min, I
SINK
= 1.2 mA
R/S/T/Z
V
CC
= V
TH
min, I
SINK
= 3.2 mA
J/L/M
V
CC
> 1.0 V, I
SINK
= 50
mA
V
OH
RESET Output Voltage High
(Push−pull, Active LOW,
CAT150xx9)
V
CC
= V
TH
max, I
SOURCE
=
−500
mA
R/S/T/Z
V
CC
= V
TH
max, I
SOURCE
=
−800
mA
J/L/M
V
CC
> V
TH
max, I
SINK
= 1.2 mA
R/S/T/Z
V
CC
> V
TH
max, I
SINK
= 3.2 mA
J/L/M
1.8 V < V
CC
≤
V
TH
min,
I
SOURCE
=
−150
mA
0.8 V
CC
0.8 V
CC
V
CC
−
1.5
0.3
0.4
V
V
140
Conditions
Conditions
Min
4.56
4.50
4.31
4.25
3.93
3.89
3.04
3.00
2.89
2.85
2.59
2.55
2.28
2.25
Min
Typ
(Note 1)
30
20
240
460
0.3
0.4
0.3
V
2.32
2.63
2.93
3.08
4.00
4.38
Typ
4.63
Max
4.70
4.75
4.45
4.50
4.06
4.10
3.11
3.15
2.96
3.00
2.66
2.70
2.35
2.38
Max
Units
ppm/°C
ms
ms
V
Units
V
V
OL
RESET Output Voltage Low
(Push−pull, Active HIGH,
CAT150xx1)
V
OH
RESET Output Voltage High
(Push−pull, Active HIGH,
CAT150xx1)
1. Production testing done at T
A
= +25°C; limits over temperature guaranteed by design only.
2. RESET output for the CAT150xx9; RESET output for the CAT150xx1.
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CAT15002, CAT15004
PIN DESCRIPTION
RESET/RESET:
Reset output is available in two versions:
CMOS Active Low (CAT150xx9) and CMOS Active High
(CAT150xx1). Both versions are push−pull outputs for high
efficiency.
SI:
The serial data input pin accepts op−codes, addresses and
data. In SPI modes (0,0) and (1,1) input data is latched on the
rising edge of the SCK clock input.
SO:
The serial data output pin is used to transfer data out of
the device. In SPI modes (0,0) and (1,1) data is shifted out
on the falling edge of the SCK clock.
SCK:
The serial clock input pin accepts the clock provided
by the host and used for synchronizing communication
between host and CAT15002/04.
CS:
The chip select input pin is used to enable/disable the
CAT15002/04. When CS is high, the SO output is tri−stated
(high impedance) and the device is in Standby Mode (unless
an internal write operation is in progress).
Every
communication session between host and CAT15002/04
must be preceded by a high to low transition and concluded
with a low to high transition of the CS input.
WP:
The write protect input pin will allow all write
operations to the device when held high. When WP pin is
tied low all write operations are inhibited.
DEVICE OPERATION
The CAT15002/04 products combine the accurate voltage
monitoring capabilities of a standalone voltage supervisor
with the high quality and reliability of standard EEPROMs
from ON Semiconductor.
RESET CONTROLLER DESCRIPTION
The reset signal is asserted LOW for the CAT150xx9 and
HIGH for the CAT150xx1 when the power supply voltage
falls below the threshold trip voltage and remains asserted
for at least 140 ms (t
PURST
) after the power supply voltage
has risen above the threshold. Reset output timing is shown
in Figure 2.
The CAT15002/04 devices protect
mPs
against brown−out
failure. Short duration V
CC
transients of 4
msec
or less and
100 mV amplitude typically do not generate a Reset pulse.
Figure 1 shows the maximum pulse duration of
negative−going V
CC
transients that do not cause a reset
condition. As the amplitude of the transient goes further
below the threshold (increasing V
TH
−
V
CC
), the maximum
pulse duration decreases. In this test, the V
CC
starts from an
initial voltage of 0.5 V above the threshold and drops below
it by the amplitude of the overdrive voltage (V
TH
−
V
CC
).
TRANSIENT DURATION [μs]
T
AMB
= 25ºC
CAT150xxZ
CAT150xxM
RESET OVERDRIVE V
TH
- V
CC
[mV]
Figure 1. Maximum Transient Duration without
Causing a Reset Pulse vs. Overdrive Voltage
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