CBTV4020
20-bit DDR SDRAM 2 : 1 MUX
Rev. 03 — 4 April 2008
Product data sheet
1. General description
This 20-bit bus switch is designed for 2.3 V to 2.7 V V
DD
operation and SSTL_2 select
input levels.
Each host port pin is multiplexed to one of two DIMM port pins. When the SEL pin is HIGH
the A DIMM port is turned on and the B DIMM port is off. The ON-state connects the host
port to the DIMM port through a 20
Ω
nominal series resistance. When the port is off a
high-impedance state exists between the Host and disabled DIMM. The DIMM port is
terminated with a 100
Ω
resistor to ground. When the SEL pin is LOW the B DIMM port is
turned on and the A DIMM port is off.
The part incorporates a very low crosstalk design. It has a very low skew between outputs
(< 50 ps) and low skew (< 50 ps) for rising and falling edges. The part has optimal
performance in DDR data bus applications.
Each switch has been optimized for connection to 1-bank or 2-bank DIMMs.
The low internal RC time constant of the switch (20
Ω ×
7 pF) allows data transfer to be
made with minimal propagation delay.
The CBTV4020 is characterized for operation from 0
°C
to +85
°C.
2. Features
I
I
I
I
I
I
I
I
I
I
I
I
SEL signal is SSTL_2 compatible
Optimized for use in Double Data Rate (DDR) SDRAM applications
Designed to be used with 400 Mbit/s 200 MHz DDR data bus
Switch ON resistance is designed to eliminate the need for series resistor to DDR
SDRAM
R
ON
~ 20
Ω
Internal 100
Ω
pull-down resistors on DIMM side when path is disabled
Low differential skew
Matched rise/fall slew rate
Low crosstalk
One DIMM select control line
Latch-up protection exceeds 500 mA per JESD78
ESD protection exceeds 1500 V HBM per JESD22-A114, 200 V MM per
JESD22-A115 and 1000 V CDM per JESD22-C101
NXP Semiconductors
CBTV4020
20-bit DDR SDRAM 2 : 1 MUX
3. Quick reference data
Table 1.
Symbol
t
PD
C
in
C
on
[1]
Quick reference data
Parameter
propagation delay
control pin capacitance
switch on capacitance
Conditions
from input DHn or DAn/DBn
to output DAn/DBn or DHn
V
I
= 2.5 V or 0 V
V
I
= 1.5 V
[1]
Min
-
-
-
Typ
140
4
-
Max
-
-
10
Unit
ps
pF
pF
[2]
[2]
The propagation delay is based on the RC time constant of the typical ON-state resistance of the switch and a load capacitance, when
driven by an ideal voltage source (zero output impedance); 20
Ω ×
7 pF. Load capacitance = 7 pF. This parameter is not production
tested.
Capacitance values are measured at 10 MHz and a bias voltage 3 V. Capacitance is not production tested.
[2]
4. Ordering information
Table 2.
Ordering information
T
amb
= 0
°
C to +85
°
C
Type number
CBTV4020EE/G
Package
Name
TFBGA72
Description
Version
plastic thin fine-pitch ball grid array package; 72 balls; body 6
×
6
×
0.8 mm SOT761-1
5. Functional diagram
DBn
Rpd
R
on
DHn
Rpd
DAn
SEL
002aad705
Fig 1.
Logic diagram (positive logic)
CBTV4020_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 4 April 2008
2 of 16
NXP Semiconductors
CBTV4020
20-bit DDR SDRAM 2 : 1 MUX
6.2 Pin description
Table 3.
Symbol
DH0
DH1
DH2
DH3
DH4
DH5
DH6
DH7
DH8
DH9
DH10
DH11
DH12
DH13
DH14
DH15
DH16
DH17
DH18
DH19
SEL
GND
V
DD
DA0
DA1
DA2
DA3
DA4
DA5
DA6
DA7
DA8
DA9
DA10
DA11
DA12
DA13
DA14
DA15
CBTV4020_3
Pin description
Pin
F2
H2
J2
J3
J5
J6
J8
J9
H9
F9
E9
C9
B9
B8
B6
B5
B3
B2
C2
E2
E3
C5, C6, D2, D9, G2, G9, H5, H6
E8, F3, F8
F1
H1
K1
K3
K4
K6
J7
K9
J10
G10
E10
C10
A10
A8
A7
A5
© NXP B.V. 2008. All rights reserved.
Description
host ports
select
ground
positive supply voltage
A DIMM ports
Product data sheet
Rev. 03 — 4 April 2008
4 of 16
NXP Semiconductors
CBTV4020
20-bit DDR SDRAM 2 : 1 MUX
Pin description
…continued
Pin
B4
A2
B1
D1
G1
J1
K2
J4
K5
K7
K8
K10
H10
F10
D10
B10
A9
B7
A6
A4
A3
A1
C1
E1
B DIMM ports
Description
A DIMM ports (continued)
Table 3.
Symbol
DA16
DA17
DA18
DA19
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
DB8
DB9
DB10
DB11
DB12
DB13
DB14
DB15
DB16
DB17
DB18
DB19
7. Functional description
Refer to
Figure 1 “Logic diagram (positive logic)”.
7.1 Function selection
Table 4.
Function selection
H = HIGH voltage level; L = LOW voltage level.
Input SEL
L
H
Function
host port = B DIMM port
A DIMM port = 100
Ω
to GND
host port = A DIMM port
B DIMM port = 100
Ω
to GND
CBTV4020_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 4 April 2008
5 of 16
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