INTEGRATED CIRCUITS
74LVT652
3.3V Octal transceiver/register,
non-inverting (3-State)
Product specification
Supersedes data of 1994 May 20
IC23 Data Handbook
1998 Feb 19
Philips
Semiconductors
Philips Semiconductors
Product specification
3.3V Octal transceiver/register, non-inverting
(3-State)
74LVT652
FEATURES
•
Independent registers for A and B buses
•
Multiplexed real-time and stored data
•
3-State outputs
•
Output capability: +64mA/–32mA
•
TTL input and output switching levels
•
Input and output interface capability to systems at 5V supply
•
Bus-hold data inputs eliminate the need for external pull-up
•
Live insertion/extraction permitted
•
No bus current loading when output is tied to 5V bus
•
Power-up 3-State
•
Power-up reset
•
Latch–up protection exceeds 500mA per JEDEC Std 17
•
ESD protection exceeds 2000V per MIL STD 883 Method 3015
and 200V per Machine Model
resistors to hold unused inputs
DESCRIPTION
The LVT652 is a high-performance BiCMOS product designed for
V
CC
operation at 3.3V.
This device combines low static and dynamic power dissipation with
high speed and high output drive.
The 74LVT652 transceiver/register consists of bus transceiver
circuits with 3-State outputs, D–type flip-flops, and control circuitry
arranged for multiplexed transmission of data directly from the input
bus or the internal registers. Data on the A or B bus will be clocked
into the registers as the appropriate clock pin goes High. Output
Enable (OEAB, OEBA) and Select (SAB, SBA) pins are provided for
bus management.
QUICK REFERENCE DATA
SYMBOL
t
PLH
t
PHL
C
IN
C
I/O
I
CCZ
PARAMETER
Propagation delay
An to Bn or Bn to An
Input capacitance
I/O capacitance
Total supply current
CONDITIONS
T
amb
= 25°C; GND = 0V
C
L
= 50pF;
V
CC
= 3.3V
V
I
= 0V or 3V
Outputs disabled; V
I/O
= 0V or 3V
Outputs disabled; V
CC
= 3.6V
TYPICAL
2.8
2.6
4
10
0.13
UNIT
ns
pF
pF
mA
ORDERING INFORMATION
PACKAGES
24-Pin Plastic SOL
24-Pin Plastic SSOP Type II
24-Pin Plastic TSSOP Type I
TEMPERATURE RANGE
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
OUTSIDE NORTH AMERICA
74LVT652 D
74LVT652 DB
74LVT652 PW
NORTH AMERICA
74LVT652 D
74LVT652 DB
74LVT652PW DH
DWG NUMBER
SOT137-1
SOT340-1
SOT355-1
PIN CONFIGURATION
CPAB
SAB
OEAB
A0
A1
A2
A3
A4
A5
1
2
3
4
5
6
7
8
9
24
23
22
21
20
19
18
17
16
15
14
13
V
CC
CPBA
SBA
OEBA
B0
B1
B2
B3
B4
B5
B6
B7
PIN DESCRIPTION
PIN NUMBER
1, 23
2, 22
SYMBOL
CPAB /
CPBA
SAB / SBA
FUNCTION
A to B clock input / B to A
clock input
A to B select input / B to A
select input
A to B Output Enable input
(active-High) /
B to A Output Enable input
(active-Low)
Data inputs/outputs (A side)
Data inputs/outputs (B side)
Ground (0V)
Positive supply voltage
3, 21
OEAB /
OEBA
4, 5, 6, 7, 8, 9,
10, 11
20, 19, 18, 17,
16, 15, 14, 13
12
A0 – A7
B0 – B7
GND
V
CC
A6 10
A7 11
GND 12
SV00051
24
1998 Feb 19
2
853-1748 18987
Philips Semiconductors
Product specification
3.3V Octal transceiver/register, non-inverting
(3-State)
74LVT652
LOGIC SYMBOL
LOGIC SYMBOL (IEEE/IEC)
21
3
EN1(BA)
EN2(AB)
C4
G5
C6
G7
4
5
6
7
8
9
10 11
23
22
1
2
A0 A1 A2 A3 A4 A5 A6 A7
23
22
2
1
CPBA
SBA
SAB
CPAB
B0 B1 B2 B3 B4 B5 B6 B7
OEAB
OEBA
3
21
4
≥1
∇1
6D
7
5
5 1
4D
20
≥1
2
19
18
17
16
15
14
13
1 7
20 19 18 17 16 15 14 13
5
SV00052
6
7
8
9
10
11
SV00053
LOGIC DIAGRAM
OEBA
OEAB
CPBA
SBA
CPAB
SAB
21
3
23
22
1
2
Detail A;
1 of 8 Channels
1D
C1
Q
20
A0
4
1D
C1
Q
B0
A1 5
A2 6
A3 7
A4 8
A5 9
A6 10
A7 11
DETAIL A X 7
19
18
17
16
15
14
13
B1
B2
B3
B4
B5
B6
B7
SV00054
1998 Feb 19
3
Philips Semiconductors
Product specification
3.3V Octal transceiver/register, non-inverting
(3-State)
74LVT652
The following examples demonstrate the four fundamental
bus-management functions that can be performed with the
74LVT652.
REAL TIME BUS TRANSFER
BUS B TO BUS A
REAL TIME BUS TRANSFER
BUS A TO BUS B
The select pins determine whether data is stored or transferred
through the device in real time.
The output enable pins determine the direction of the data flow.
STORAGE FROM
A, B, OR A AND B
TRANSFER STORED DATA
TO A OR B
A
B
A
B
A
B
A
B
OEAB OEBA CPAB CPBA SAB SBA
L
L
X
X
X
L
FUNCTION TABLE
INPUTS
OEAB
L
L
X
H
L
L
L
L
H
H
H
H
L
X
↑
*
**
=
=
=
=
OEBA
H
H
H
H
X
L
L
L
H
H
L
CPAB
H or L
↑
↑
↑
H or L
↑
X
X
X
H or L
H or L
CPBA
H or L
↑
H or L
↑
↑
↑
X
H or L
X
X
H or L
SAB
X
X
X
**
X
X
X
X
L
H
H
SBA
X
X
X
X
X
**
L
H
X
X
H
An
Input
Input
Unspecified**
Output*
Output
Input
Output
DATA I/O
Bn
Input
Unspecified**
Output*
Input
Input
Output
Output
OPERATING MODE
Isolation
Store A and B data
Store A, Hold B
Store A in both registers
Hold A, Store B
Store B in both registers
Real time B data to A bus
Stored B data to A bus
Real time A data to B bus
Store A data to B bus
Stored A data to B bus
Stored B data to A bus
High voltage level
Low voltage level
Don’t care
Low-to-High clock transition
The data output function may be enabled or disabled by various signals at the OEBA and OEAB inputs. Data input functions are always
enabled, i.e., data at the bus pins will be stored on every Low-to-High transition of the clock.
If both Select controls (SAB and SBA) are Low, then clocks can occur simultaneously. If either Select control is High, the clocks must be
staggered in order to load both registers.
}
H
H
OEAB OEBA CPAB CPBA SAB SBA
X
X
L
X
}
X
L
L
H
X
H
OEAB OEBA CPAB CPBA SAB SBA
↑
X
↑
X
↑
↑
X
X
X
X
X
X
}
H
L
OEAB OEBA CPAB CPBA SAB SBA
H|L H|L
H
H
}
SV00055
1998 Feb 19
4
Philips Semiconductors
Product specification
3.3V Octal transceiver/register, non-inverting
(3-State)
74LVT652
ABSOLUTE MAXIMUM RATINGS
1,2
SYMBOL
V
CC
I
IK
V
I
I
OK
V
OUT
I
O
OUT
T
stg
PARAMETER
DC supply voltage
DC input diode current
DC input voltage
3
DC output diode current
DC output voltage
3
DC output current
Output in High state
Storage temperature range
–64
–65 to +150
°C
V
O
< 0
Output in Off
Output in Low state
V
I
< 0
CONDITIONS
RATING
–0.5 to +4.6
–50
–0.5 to +7.0
–50
–0.5 to +7.0
128
mA
UNIT
V
mA
V
mA
V
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C.
3. The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
LIMITS
SYMBOL
V
CC
V
I
V
IH
V
IL
I
OH
I
OL
DC supply voltage
Input voltage
High-level input voltage
Input voltage
High-level output current
Low-level output current
Low-level output current; current duty cycle
≤
50%; f
≥
1kHz
∆t/∆v
T
amb
Input transition rise or fall rate; Outputs enabled
Operating free-air temperature range
–40
PARAMETER
MIN
2.7
0
2.0
0.8
–32
32
64
10
+85
ns/V
°C
MAX
3.6
5.5
V
V
V
V
mA
mA
UNIT
1998 Feb 19
5
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