DISCRETE SEMICONDUCTORS
DATA SHEET
BF1201; BF1201R; BF1201WR
N-channel dual-gate PoLo
MOS-FETs
Product specification
Supersedes data of 1999 Dec 01
2000 Mar 29
NXP Semiconductors
Product specification
N-channel dual-gate PoLo MOS-FETs
FEATURES
Short channel transistor with high
forward transfer admittance to input
capacitance ratio
Low noise gain controlled amplifier
Partly internal self-biasing circuit to
ensure good cross-modulation
performance during AGC and good
DC stabilization.
APPLICATIONS
VHF and UHF applications with
3 to 9 V supply voltage, such as
digital and analogue television
tuners and professional
communications equipment.
handbook, 2 columns
4
BF1201; BF1201R;
BF1201WR
PINNING
PIN
1
2
3
4
DESCRIPTION
source
drain
gate 2
gate 1
Top view
MSB035
handbook, 2 columns
3
4
2
1
BF1201R marking code:
LBp
Fig.2
Simplified outline
(SOT143R).
3
lfpage
3
4
DESCRIPTION
Enhancement type N-channel
field-effect transistor with source and
substrate interconnected. Integrated
diodes between gates and source
protect against excessive input
voltage surges. The BF1201,
BF1201R and BF1201WR are
encapsulated in the SOT143B,
SOT143R and SOT343R plastic
packages respectively.
QUICK REFERENCE DATA
SYMBOL
V
DS
I
D
P
tot
y
fs
C
ig1-ss
C
rss
F
X
mod
T
j
PARAMETER
drain-source voltage
drain current
total power dissipation
forward transfer admittance
input capacitance at gate 1
reverse transfer capacitance
noise figure
cross-modulation
operating junction temperature
CAUTION
This product is supplied in anti-static packing to prevent damage caused by electrostatic discharge during transport
and handling.
2000 Mar 29
2
f = 1 MHz
f = 400 MHz
input level for k = 1% at
40 dB AGC
CONDITIONS
23
105
MIN.
28
2.6
15
1
TYP.
MAX.
10
30
200
35
3.1
30
1.8
150
UNIT
V
mA
mW
mS
pF
fF
dB
dBV
C
1
Top view
2
MSB014
2
Top view
1
MSB842
BF1201 marking code:
LAp.
BF1201WR marking code:
LA
Fig.1
Simplified outline
(SOT143B).
Fig.3
Simplified outline
(SOT343R).
NXP Semiconductors
Product specification
N-channel dual-gate PoLo MOS-FETs
BF1201; BF1201R; BF1201WR
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134).
SYMBOL
V
DS
I
D
I
G1
I
G2
P
tot
PARAMETER
drain-source voltage
drain current (DC)
gate 1 current
gate 2 current
total power dissipation
BF1201; BF1201R
BF1201WR
T
stg
T
j
Note
1. T
s
is the temperature of the soldering point of the source lead.
THERMAL CHARACTERISTICS
SYMBOL
R
th j-s
BF1201; BF1201R
BF1201WR
PARAMETER
thermal resistance from junction to soldering point
185
155
K/W
K/W
VALUE
UNIT
storage temperature
operating junction temperature
T
s
113
C;
note 1
T
s
109
C;
note 1
65
200
200
+150
150
mW
mW
C
C
CONDITIONS
MIN.
MAX.
10
30
10
10
V
mA
mA
mA
UNIT
250
handbook, halfpage
Ptot
(mW)
200
MCD934
(2)
(1)
150
100
50
0
0
50
100
150
Ts (°C)
200
(1) BF1201WR.
(2) BF1201 and BF1201R.
Fig.4 Power derating curve.
2000 Mar 29
3
NXP Semiconductors
Product specification
N-channel dual-gate PoLo MOS-FETs
STATIC CHARACTERISTICS
T
j
= 25
C;
unless otherwise specified.
SYMBOL
V
(BR)DSS
PARAMETER
drain-source breakdown voltage
BF1201; BF1201R; BF1201WR
CONDITIONS
V
G1-S
= V
G2-S
= 0; I
D
= 10
A
V
G2-S
= V
DS
= 0; I
G1-S
= 10 mA
V
G1-S
= V
DS
= 0; I
G2-S
= 10 mA
V
G2-S
= V
DS
= 0; I
S-G1
= 10 mA
V
G1-S
= V
DS
= 0; I
S-G2
= 10 mA
V
G2-S
= 4 V; V
DS
= 5 V; I
D
= 100
A
V
G1-S
= V
DS
= 5 V; I
D
= 100
A
V
G2-S
= 4 V; V
DS
= 5 V; R
G1
= 62 k;
note 1
V
G2-S
= V
DS
= 0; V
G1-S
= 5 V
V
G1-S
= V
DS
= 0; V
G2-S
= 4 V
MIN.
10
6
6
0.5
0.5
0.3
0.3
11
MAX.
1.5
1.5
1.0
1.2
19
50
20
UNIT
V
V
V
V
V
V
V
mA
nA
nA
V
(BR)G1-SS
gate 1-source breakdown voltage
V
(BR)G2-SS
gate 2-source breakdown voltage
V
(F)S-G1
V
(F)S-G2
V
G1-S(th)
V
G2-S(th)
I
DSX
I
G1-SS
I
G2-SS
Note
1. R
G1
connects G
1
to V
GG
= 5 V.
forward source-gate 1 voltage
forward source-gate 2 voltage
gate 1-source threshold voltage
gate 2-source threshold voltage
drain-source current
gate 1 cut-off current
gate 2 cut-off current
DYNAMIC CHARACTERISTICS
Common source; T
amb
= 25
C;
V
G2-S
= 4 V; V
DS
= 5 V; I
D
= 15 mA; unless otherwise specified.
SYMBOL
y
fs
C
ig1-ss
C
ig2-ss
C
oss
C
rss
F
PARAMETER
forward transfer admittance
input capacitance at gate 1
input capacitance at gate 2
output capacitance
noise figure
f = 1 MHz
f = 1 MHz
f = 1 MHz
f = 10.7 MHz; G
S
= 20 mS; B
S
= 0
f = 400 MHz; Y
S
= Y
S opt
f = 800 MHz; Y
S
= Y
S opt
G
tr
power gain
f = 200 MHz; G
S
= 2 mS; B
S
= B
S opt
;
G
L
= 0.5 mS; B
L
= B
L opt
;
f = 400 MHz; G
S
= 2 mS; B
S
= B
S opt
;
G
L
= 1 mS; B
L
= B
L opt
;
f = 800 MHz; G
S
= 3.3 mS; B
S
= B
S opt
;
G
L
= 1 mS; B
L
= B
L opt
;
X
mod
cross-modulation
input level for k = 1%; f
w
= 50 MHz;
f
unw
= 60 MHz; note 1
at 0 dB AGC
at 10 dB AGC
at 40 dB AGC
Note
1. Measured in Fig.21 test circuit.
90
105
95
dBV
dBV
dBV
CONDITIONS
pulsed; T
j
= 25
C
MIN.
23
TYP.
28
2.6
1.1
0.9
15
5
1
1.9
33.5
29
24
MAX.
35
3.1
30
7
1.8
2.5
UNIT
mS
pF
pF
pF
fF
dB
dB
dB
dB
dB
dB
reverse transfer capacitance f = 1 MHz
2000 Mar 29
4
NXP Semiconductors
Product specification
N-channel dual-gate PoLo MOS-FETs
BF1201; BF1201R; BF1201WR
handbook, halfpage
25
MCD935
ID
VG2-S
=
4 V
(mA)
20
3.5 V
3V
handbook, halfpage
24
MCD936
ID
(mA)
16
VG1-S
=
1.8 V
1.7 V
1.6 V
1.5 V
1.4 V
2.5 V
15
2V
10
8
1.5 V
5
1V
0
0
0.5
1
1.5
2
2.5
VG1-S (V)
0
0
2
4
6
8
1.3 V
1.2 V
10
VDS (V)
V
DS
= 5 V.
T
j
= 25
C.
V
G2-S
= 4 V.
T
j
= 25
C.
Fig.5 Transfer characteristics; typical values.
Fig.6 Output characteristics; typical values.
handbook, halfpage
100
MCD937
IG1
(μA)
VG2-S
=
4 V
handbook, halfpage
40
MCD938
3.5 V
yfs
(mS)
VG2-S
=
4 V
3.5 V
30
80
3V
60
2.5 V
40
2V
20
1.5 V
0
0
0.5
1
1.5
2
2.5
VG1-S (V)
20
3V
10
2V
2.5 V
0
0
5
10
15
20
25
ID (mA)
V
DS
= 5 V.
T
j
= 25
C.
V
DS
= 5 V.
T
j
= 25
C.
Fig.7
Gate 1 current as a function of gate 1
voltage; typical values.
Fig.8
Forward transfer admittance as a function
of drain current; typical values.
2000 Mar 29
5
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