2.5 V or 3.3 V, 200 MHz, 1:18 Clock Distribution Buffer
Features
■
■
■
■
■
■
Functional Description
The CY29940 is a low-voltage 200 MHz clock distribution buffer
with the capability to select either a differential LVPECL or a
LVCMOS/LVTTL compatible input clock. The two clock sources
can be used to provide for a test clock as well as the primary
system clock. All other control inputs are LVCMOS/LVTTL
compatible. The eighteen outputs are 2.5 V or 3.3 V
LVCMOS/LVTTL compatible and can drive 50
series or parallel
terminated transmission lines. For series terminated
transmission lines, each output can drive one or two traces giving
the device an effective fanout of 1:36. Low output-to-output
skews make the CY29940 an ideal clock distribution buffer for
nested clock trees in the most demanding of synchronous
systems.
For a complete list of related documentation,
click here.
200 MHz clock support
LVPECL or LVCMOS/LVTTL clock input
LVCMOS/LVTTL compatible inputs
18 clock outputs: drive up to 36 clock lines
60 ps typical output-to-output skew
Dual or single supply operation:
❐
3.3 V core and 3.3 V outputs
❐
3.3 V core and 2.5 V outputs
❐
2.5 V core and 2.5 V outputs
Pin compatible with MPC940L, MPC9109
Available in Commercial and Industrial temperature
32-pin TQFP package
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■
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Block Diagram
VDD
PECL_CLK
PECL_CLK#
TCLK
TCLK_SEL
0
1
VDDC
18
Q0-Q17
Cypress Semiconductor Corporation
Document Number: 38-07283 Rev. *J
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised November 22, 2017
CY29940
Pin Configuration
VDDC
VSS
25
Q0
Q1
Q2
Q3
28
Q4
27
Q5
26
32
31
30
29
VSS
VSS
TCLK
TCLK_SEL
PECL_CLK
PECL_CLK#
VDD
VDDC
1
2
3
4
5
6
7
8
CY29940
10
11
12
13
14
15
16
9
24
23
22
21
20
19
18
17
Q6
Q7
Q8
VDD
Q9
Q10
Q11
VSS
VSS
Pin Description
Pin
5
6
3
9, 10, 11, 13, 14,
15, 18, 19, 20, 22,
23, 24, 26, 27, 28,
30, 31, 32
4
8, 16, 29
7, 21
1, 2, 12, 17, 25
Name
PECL_CLK
PECL_CLK#
TCLK
Q(17:0)
VDDC
PWR
I/O
[1]
I, PU
I, PD
I, PD
O
PECL input clock
PECL input clock
External reference/test clock input
Clock outputs
Description
TCLK_SEL
VDDC
VDD
VSS
I, PD
Clock Select Input. When LOW, PECL clock is selected and when HIGH
TCLK is selected.
3.3 V or 2.5 V power supply for output clock buffers
3.3 V or 2.5 V power supply
Common ground
Note
1. PD = Internal Pull-Down, PU = Internal Pull-up
Document Number: 38-07283 Rev. *J
VDDC
Q17
Q16
Q15
Q14
Q13
Q12
Page 2 of 10
CY29940
Maximum Ratings
Exceeding the maximum ratings
[2]
may impair the useful life of
the device. User guidelines are not tested.
Maximum input voltage relative to V
SS
.............. V
SS
– 0.3 V
Maximum input voltage relative to V
DD
.............. V
DD
+ 0.3 V
Storage temperature ................................ –65
C
to +150
C
Operating temperature .............................. –40
C
to +85
C
Maximum ESD protection .............................................. 2 kV
Maximum power supply ................................................ 5.5 V
Maximum input current ............................................. ±20 mA
This device contains circuitry to protect the inputs against
damage due to high static voltages or electric field; however,
precautions should be taken to avoid application of any voltage
higher than the maximum rated voltages to this circuit. For proper
operation, V
in
and V
out
should be constrained to the range:
V
SS
< (V
in
or V
out
) < V
DD
Unused inputs must always be tied to an appropriate logic
voltage level (either V
SS
or V
DD
).
DC Parameters
V
DD
= 3.3 V ± 5% or 2.5 V ± 5%, V
DDC
= 3.3 V ± 5% or 2.5 V ± 5%, T
A
= –40
C
to +85
C
Parameter
[2]
V
IL
V
IH
I
IL
I
IH
V
PP
V
CMR
V
OL
V
OH
I
DDQ
I
DD
Description
Input low voltage
Input high voltage
Input low current
[3]
Input high current
[3]
Peak-to-peak input voltage
PECL_CLK
Common mode range
[4]
PECL_CLK
Output low voltage
[5, 6, 7]
Output high voltage
[5, 6, 7]
Quiescent supply current
Dynamic supply current
V
DD
= 3.3 V, Outputs at 150 MHz, C
L
= 15 pF
V
DD
= 3.3 V, Outputs at 200 MHz, C
L
= 15 pF
V
DD
= 2.5 V, Outputs at 150 MHz, C
L
= 15 pF
V
DD
= 2.5 V, Outputs at 200 MHz, C
L
= 15 pF
Z
out
C
in
Output impedance
Input capacitance
V
DD
= 3.3 V
V
DD
= 2.5 V
V
DD
= 3.3 V
V
DD
= 2.5 V
I
OL
= 20 mA
I
OH
= –20 mA, V
DDC
= 3.3 V
I
OH
= –20 mA, V
DDC
= 2.5 V
Conditions
Min
V
SS
2.0
–
–
500
V
DD
– 1.4
V
DD
– 1.0
–
2.4
1.8
–
–
–
–
–
8
10
–
Typ
–
–
–
–
–
–
–
–
–
–
5
285
335
200
240
12
15
4
Max
0.8
V
DD
–200
200
1000
V
DD
– 0.6
V
DD
– 0.6
0.5
–
–
7
–
–
–
–
16
20
–
pF
Unit
V
V
µA
µA
mV
V
V
V
V
V
mA
mA
Thermal Resistance
Parameter
[8]
θ
JA
θ
JC
Description
Thermal resistance
(junction to ambient)
Thermal resistance
(junction to case)
Test Conditions
Test conditions follow standard test methods and
procedures for measuring thermal impedance, in
accordance with EIA/JESD51.
32-pin TQFP
67
28
Unit
°C/W
°C/W
Notes
2.
Multiple Supplies:
The Voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is not required.
3. Inputs have pull-up/pull-down resistors that effect input current.
4. The VCMR is the difference from the most positive side of the differential input signal. Normal operation is obtained when the “High” input is within the VCMR range
and the input lies within the VPP specification. Driving series or parallel terminated 50
(or 50
to V
DD
/2) transmission lines
5. Outputs driving 50
transmission
lines.
6. See
Figure 1 on page 5
and
Figure 2 on page 5.
7. 50% input duty cycle.
8. These parameters are guaranteed by design and are not tested.
Document Number: 38-07283 Rev. *J
Page 3 of 10
CY29940
AC Parameters
[9]
V
DD
= 3.3 V ± 5% or 2.5 V ± 5%, V
DDC
= 3.3 V ± 5% or 2.5 V ± 5%, T
A
= –40
C
to +85
C
Parameter
F
max
t
PD
Description
Input frequency
PECL_CLK to Q Delay
[10, 11, 12]
150 MHz V
DD
= 3.3 V, 85
C
V
DD
= 3.3 V, 70
C
V
DD
= 2.5 V, 85
C
V
DD
= 2.5 V, 70
C
t
PD
LVCMOS to Q Delay
[10, 11, 12]
150 MHz
V
DD
= 3.3 V, 85
C
V
DD
= 3.3 V, 70
C
V
DD
= 2.5 V, 85
C
V
DD
= 2.5 V, 70
C
t
J
FoutDC
T
skew
T
skew
(pp)
T
skew
(pp)
T
skew
(pp)
t
R
/t
F
Total jitter
Output duty cycle
[10, 11, 13]
Output-to-output skew
[10, 11]
Part-to-part skew
[14]
Part-to-part skew
[14]
Part-to-part skew
[15]
Output clocks rise/fall time
[10, 11]
V
DD
= 3.3 V @ 150 MHz
FCLK < 134 MHz
FCLK > 134 MHz
V
DD
= 3.3 V
V
DD
= 2.5 V
PECL, V
DDC
= 3.3 V
PECL, V
DDC
= 2.5 V
TCLK, V
DDC
= 3.3 V
TCLK, V
DDC
= 2.5 V
PECL_CLK
TCLK
0.7 V to 2.0 V, V
DDC
= 3.3 V
0.5 V to 1.8 V, V
DDC
= 2.5 V
Conditions
–
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
Min
–
2.0
2.1
1.9
2.0
2.5
2.6
2.5
2.6
1.9
2.0
1.8
1.8
2.5
2.5
2.3
2.3
–
–
–
–
–
–
–
–
–
–
–
0.3
0.3
Typ
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
60
–
–
–
–
–
–
–
–
–
Max
200
3.2
3.4
3.1
3.2
5.2
5
5
5
3
3.2
2.9
3.1
4
4
3.8
3.8
10
55
60
150
200
1.4
2.2
1.2
1.7
850
750
1.1
1.2
ns
ps
ns
ns
ps
ps
%
ns
Unit
MHz
ns
Notes
9. Parameters are guaranteed by design and characterization. Not 100% tested in production. All parameters specified with loaded outputs.
10. Outputs driving 50
transmission
lines.
11. See
Figure 1 on page 5
and
Figure 2 on page 5.
12. Parameters tested @ 150 MHz.
13. 50% input duty cycle.
14. Across temperature and voltage ranges, includes output skew.
15. For a specific temperature and voltage, includes output skew.
Document Number: 38-07283 Rev. *J
Page 4 of 10
CY29940
Figure 1. LVCMOS_CLK CY29940 Test Reference for V
CC
= 3.3 V and V
CC
= 2.5 V
CY29940 DUT
Pulse
Generator
Z = 50 ohm
Zo = 50 ohm
R
T
= 50 ohm
Zo = 50 ohm
R
T
= 50 ohm
VTT
VTT
Figure 2. PECL_CLK CY29940 Test Reference for V
CC
= 3.3 V and V
CC
= 2.5 V
Zo = 50 ohm
Differential
Pulse
Generator
Z = 50 ohm
CY29940 DUT
Zo = 50 ohm
Zo = 50 ohm
R
T
= 50 ohm
R
T
= 50 ohm
VTT
VTT
Figure 3. Propagation Delay (TPD) Test Reference
PECL_CLK
PECL_CLK
V
PP
V
CMR
VCC
Q
VCC /2
t
PD
GND
Figure 4. LVCMOS Propagation Delay (TPD) Test Reference
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