NTD24N06L, STD24N06L
Power MOSFET
24 Amps, 60 Volts
Logic Level, N−Channel DPAK
Designed for low voltage, high speed switching applications in
power supplies, converters and power motor controls and bridge
circuits.
Features
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•
AEC−Q101 Qualified and PPAP Capable
−
STD24N06L
•
These Devices are Pb−Free and are RoHS Compliant
Typical Applications
24 AMPERES, 60 VOLTS
R
DS(on)
= 0.036
W (Typ)
N−Channel
D
•
•
•
•
Power Supplies
Converters
Power Motor Controls
Bridge Circuits
G
S
MAXIMUM RATINGS
(T
J
= 25°C unless otherwise noted)
Rating
Drain−to−Source Voltage
Drain−to−Gate Voltage (R
GS
= 10 MW)
Gate−to−Source Voltage
−
Continuous
−
Non−repetitive (t
p
v10
ms)
Drain Current
−
Continuous @ T
A
= 25°C
−
Continuous @ T
A
= 100°C
−
Single Pulse (t
p
v10
ms)
Symbol
V
DSS
V
DGR
V
GS
V
GS
I
D
I
D
Value
60
60
"15
"20
24
10
72
62.5
0.42
1.88
1.36
−55
to
+175
162
Unit
Vdc
Vdc
Vdc
4
Adc
Apk
W
W/°C
W
W
°C
mJ
1
R
qJC
R
qJA
R
qJA
T
L
2.4
80
110
260
°C/W
2
4
DPAK
CASE 369D
(Straight Lead)
STYLE 2
3
1 2 3
Gate Drain Source
°C
Y
WW
24N6L
G
= Year
= Work Week
= Device Code
= Pb−Free Package
1 2
DPAK
CASE 369C
(Surface Mount)
STYLE 2
MARKING DIAGRAMS
& PIN ASSIGNMENTS
4
Drain
YWW
24
N6LG
4
Drain
YWW
24
N6LG
3
I
DM
P
D
Total Power Dissipation @ T
A
= 25°C
Derate above 25°C
Total Power Dissipation @ T
A
= 25°C (Note 1)
Total Power Dissipation @ T
A
= 25°C (Note 2)
Operating and Storage Temperature Range
Single Pulse Drain−to−Source Avalanche
Energy
−
Starting T
J
= 25°C
(V
DD
= 50 Vdc, V
GS
= 5.0 Vdc,
L = 1.0 mH, I
L
(pk) = 18 A, V
DS
= 60 Vdc)
Thermal Resistance
−
Junction−to−Case
−
Junction−to−Ambient (Note 1)
−
Junction−to−Ambient (Note 2)
Maximum Lead Temperature for Soldering
Purposes, 1/8 in from case for 10 seconds
2
1
3
Drain
Gate
Source
T
J
, T
stg
E
AS
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. When surface mounted to an FR4 board using 0.5 sq. in. pad size.
2. When surface mounted to an FR4 board using minimum recommended pad
size.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
©
Semiconductor Components Industries, LLC, 2011
October, 2011
−
Rev. 3
1
Publication Order Number:
NTD24N06L/D
NTD24N06L, STD24N06L
ELECTRICAL CHARACTERISTICS
(T
J
= 25°C unless otherwise noted)
Characteristic
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage (Note 3)
(V
GS
= 0 Vdc, I
D
= 250
mAdc)
Temperature Coefficient (Positive)
Zero Gate Voltage Drain Current
(V
DS
= 60 Vdc, V
GS
= 0 Vdc)
(V
DS
= 60 Vdc, V
GS
= 0 Vdc, T
J
= 150°C)
Gate−Body Leakage Current (V
GS
=
±
15 Vdc, V
DS
= 0 Vdc)
ON CHARACTERISTICS
(Note 3)
Gate Threshold Voltage (Note 3)
(V
DS
= V
GS
, I
D
= 250
mAdc)
Threshold Temperature Coefficient (Negative)
Static Drain−to−Source On−Resistance (Note 3)
(V
GS
= 5.0 Vdc, I
D
= 10 Adc)
(V
GS
= 5.0 Vdc, I
D
= 12 Adc)
Static Drain−to−Source On−Resistance (Note 3)
(V
GS
= 5.0 Vdc, I
D
= 20 Adc)
(V
GS
= 5.0 Vdc, I
D
= 24 Adc)
(V
GS
= 5.0 Vdc, I
D
= 12 Adc, T
J
= 150°C)
Forward Transconductance (Note 3) (V
DS
= 7.0 Vdc, I
D
= 12 Adc)
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
Transfer Capacitance
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
Fall Time
Gate Charge
(V
DD
= 30 Vdc, I
D
= 24 Adc,
V
GS
= 5.0 Vdc,
R
G
= 9.1
W)
(Note 3)
(V
DS
= 48 Vdc, I
D
= 24 Adc,
V
GS
= 5.0 Vdc) (Note 3)
(V
DS
= 25 Vdc, V
GS
= 0 Vdc,
f = 1.0 MHz)
C
iss
C
oss
C
rss
t
d(on)
t
r
t
d(off)
t
f
Q
T
Q
1
Q
2
V
SD
t
rr
t
a
t
b
Q
RR
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
814
258
80
9.4
97
23
52
16
3.4
11
0.93
0.95
0.86
49
30
20
0.084
1140
360
115
20
200
50
100
32
−
−
1.1
−
−
−
−
−
−
mC
Vdc
nC
ns
pF
V
GS(th)
1.0
−
−
−
−
−
−
−
1.7
5.0
36
36
0.9
0.9
0.78
19
2.0
−
45
−
1.2
−
−
−
Vdc
mV/°C
mW
V
(BR)DSS
60
−
−
−
−
71.9
69.6
−
−
−
−
−
1.0
10
±100
Vdc
mV/°C
mAdc
Symbol
Min
Typ
Max
Unit
I
DSS
I
GSS
nAdc
R
DS(on)
V
DS(on)
Vdc
g
FS
mhos
SWITCHING CHARACTERISTICS
(Note 4)
SOURCE−DRAIN DIODE CHARACTERISTICS
Forward On−Voltage
(I
S
= 20 Adc, V
GS
= 0 Vdc) (Note 3)
(I
S
= 24 Adc, V
GS
= 0 Vdc)
(I
S
= 24 Adc, V
GS
= 0 Vdc, T
J
= 150°C)
(I
S
= 24 Adc, V
GS
= 0 Vdc,
dI
S
/dt = 100 A/ms) (Note 3)
Reverse Recovery Time
ns
Reverse Recovery Stored Charge
3. Pulse Test: Pulse Width
≤
300
ms,
Duty Cycle
≤
2%.
4. Switching characteristics are independent of operating junction temperatures.
ORDERING INFORMATION
Device
NTD24N06LT4G
STD24N06LT4G
Package
DPAK
(Pb−Free)
DPAK
(Pb−Free)
Shipping
†
2500 / Tape & Reel
2500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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2
NTD24N06L, STD24N06L
50
I
D
, DRAIN CURRENT (AMPS)
V
GS
= 10 V
40
30
20
10
8V
6V
4V
50
I
D
, DRAIN CURRENT (AMPS)
4.5 V
V
DS
≥
10 V
40
30
20
10
T
J
= 25°C
5V
T
J
=
−55°C
T
J
= 100°C
3.5 V
3V
0
0
1
2
3
4
0
1.6
2.4
3.2
4
4.8
V
DS
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
V
GS
, GATE−TO−SOURCE VOLTAGE (VOLTS)
Figure 1. On−Region Characteristics
R
DS(on)
, DRAIN−TO−SOURCE RESISTANCE (W)
R
DS(on)
, DRAIN−TO−SOURCE RESISTANCE (W)
0.1
0.08
0.06
0.04
0.02
0
T
J
= 100°C
0.1
Figure 2. Transfer Characteristics
V
GS
= 5 V
V
GS
= 10 V
0.08
0.06
T
J
= 100°C
0.04
0.02
T
J
=
−55°C
0
0
10
20
30
40
50
T
J
= 25°C
T
J
= 25°C
T
J
=
−55°C
0
10
20
30
40
50
I
D
, DRAIN CURRENT (AMPS)
I
D
, DRAIN CURRENT (AMPS)
Figure 3. On−Resistance versus
Gate−to−Source Voltage
R
DS(on)
, DRAIN−TO−SOURCE RESISTANCE
(NORMALIZED)
2
1.8
1.6
1.4
1.2
1
0.8
0.6
−50 −25
1
I
D
= 12 A
V
GS
= 5 V
10000
Figure 4. On−Resistance versus Drain Current
and Gate Voltage
V
GS
= 0 V
T
J
= 150°C
I
DSS
, LEAKAGE (nA)
1000
100
T
J
= 100°C
0
25
50
75
100
125
150
175
0
10
20
30
40
50
60
T
J
, JUNCTION TEMPERATURE (°C)
V
DS
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−to−Source Leakage Current
versus Voltage
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3
NTD24N06L, STD24N06L
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge
controlled. The lengths of various switching intervals (Dt)
are determined by how fast the FET input capacitance can
be charged by current from the generator.
The published capacitance data is difficult to use for
calculating rise and fall because drain−gate capacitance
varies greatly with applied voltage. Accordingly, gate
charge data is used. In most cases, a satisfactory estimate of
average input current (I
G(AV)
) can be made from a
rudimentary analysis of the drive circuit so that
t = Q/I
G(AV)
During the rise and fall time interval when switching a
resistive load, V
GS
remains virtually constant at a level
known as the plateau voltage, V
SGP
. Therefore, rise and fall
times may be approximated by the following:
t
r
= Q
2
x R
G
/(V
GG
−
V
GSP
)
t
f
= Q
2
x R
G
/V
GSP
where
V
GG
= the gate drive voltage, which varies from zero to V
GG
R
G
= the gate drive resistance
and Q
2
and V
GSP
are read from the gate charge curve.
During the turn−on and turn−off delay times, gate current is
not constant. The simplest calculation uses appropriate
values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
t
d(on)
= R
G
C
iss
In [V
GG
/(V
GG
−
V
GSP
)]
t
d(off)
= R
G
C
iss
In (V
GG
/V
GSP
)
2800
2400
C, CAPACITANCE (pF)
2000
1600
1200
800
400
0
C
rss
10
5
V
GS
0
V
DS
5
10
15
20
25
C
rss
C
iss
C
oss
C
iss
The capacitance (C
iss
) is read from the capacitance curve at
a voltage corresponding to the off−state condition when
calculating t
d(on)
and is read at a voltage corresponding to the
on−state when calculating t
d(off)
.
At high switching speeds, parasitic circuit elements
complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring
which is common to both the drain and gate current paths,
produces a voltage at the source which reduces the gate drive
current. The voltage is determined by Ldi/dt, but since di/dt
is a function of drain current, the mathematical solution is
complex. The MOSFET output capacitance also
complicates the mathematics. And finally, MOSFETs have
finite internal gate resistance which effectively adds to the
resistance of the driving source, but the internal resistance
is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate
resistance (Figure 9) shows how typical switching
performance is affected by the parasitic circuit elements. If
the parasitics were not present, the slope of the curves would
maintain a value of unity regardless of the switching speed.
The circuit used to obtain the data is constructed to minimize
common inductance in the drain and gate circuit loops and
is believed readily achievable with board mounted
components. Most power electronic loads are inductive; the
data in the figure is taken with a resistive load, which
approximates an optimally snubbed inductive load. Power
MOSFETs may be safely operated into an inductive load;
however, snubbing reduces switching losses.
V
DS
= 0 V
V
GS
= 0 V
T
J
= 25°C
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
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4
NTD24N06L, STD24N06L
VGS , GATE−TO−SOURCE VOLTAGE (VOLTS)
6
5
4
3
2
1
0
I
D
= 24 A
T
J
= 25°C
0
4
8
12
16
Q
G
, TOTAL GATE CHARGE (nC)
20
1
1
Q
1
Q
T
Q
2
V
GS
t, TIME (ns)
100
t
r
t
f
t
d(off)
10
t
d(on)
V
DS
= 30 V
I
D
= 24 A
V
GS
= 5 V
10
R
G
, GATE RESISTANCE (OHMS)
100
1000
Figure 8. Gate−To−Source and Drain−To−Source
Voltage versus Total Charge
Figure 9. Resistive Switching Time
Variation versus Gate Resistance
DRAIN−TO−SOURCE DIODE CHARACTERISTICS
24
IS, SOURCE CURRENT (AMPS)
20
16
12
8
4
0
V
GS
= 0 V
T
J
= 25°C
0.6
0.68
0.76
0.84
0.92
V
SD
, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
1
Figure 10. Diode Forward Voltage versus Current
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define
the maximum simultaneous drain−to−source voltage and
drain current that a transistor can handle safely when it is
forward biased. Curves are based upon maximum peak
junction temperature and a case temperature (T
C
) of 25°C.
Peak repetitive pulsed power limits are determined by using
the thermal response data in conjunction with the procedures
discussed in AN569, “Transient Thermal Resistance
−
General Data and Its Use.”
Switching between the off−state and the on−state may
traverse any load line provided neither rated peak current
(I
DM
) nor rated voltage (V
DSS
) is exceeded and the
transition time (t
r
,t
f
) do not exceed 10
ms.
In addition the total
power averaged over a complete switching cycle must not
exceed (T
J(MAX)
−
T
C
)/(R
qJC
).
A Power MOSFET designated E−FET can be safely used
in switching circuits with unclamped inductive loads. For
reliable operation, the stored energy from circuit inductance
dissipated in the transistor while in avalanche must be less
than the rated limit and adjusted for operating conditions
differing from those specified. Although industry practice is
to rate in terms of energy, avalanche energy capability is not
a constant. The energy rating decreases non−linearly with an
increase of peak current in avalanche and peak junction
temperature.
Although many E−FETs can withstand the stress of
drain−to−source avalanche at currents up to rated pulsed
current (I
DM
), the energy rating is specified at rated
continuous current (I
D
), in accordance with industry custom.
The energy rating must be derated for temperature as shown
in the accompanying graph (Figure 12). Maximum energy at
currents below rated continuous I
D
can safely be assumed to
equal the values indicated.
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