Crystal or Differential-to-LVCMOS/
LVTTL Clock Buffer
Datasheet
8L30110
Description
The 8L30110 is a low skew, 1-to-10 LVCMOS / LVTTL Fanout
Buffer. The low impedance LVCMOS/LVTTL outputs are designed
to drive 50 series or parallel terminated transmission lines.
The 8L30110 is characterized at full 3.3V and 2.5V, mixed
3.3V/2.5V, 3.3V/1.8V, 3.3V/1.5V, 2.5V/1.8V and 2.5V/1.5V output
operating supply modes. The input clock is selected from two
differential clock inputs or a crystal input. The differential input can
be wired to accept a single-ended input. The internal oscillator
circuit is automatically disabled if the crystal input is not selected.
Features
• Ten LVCMOS / LVTTL outputs up to 200MHz
• Differential input pair can accept the following differential input
levels: LVPECL, LVDS, HCSL
• Crystal Oscillator Interface
• Crystal input frequency range: 8MHz to 50MHz
• Output skew: 63ps (typical)
• Additive RMS phase jitter: 22fs (typical)
• Power supply modes:
Core / Output
3.3V / 3.3V
3.3V / 2.5V
3.3V / 1.8V
3.3V / 1.5V
2.5V / 2.5V
2.5V / 1.8V
2.5V / 1.5V
• -40°C to 85°C ambient operating temperature
• Lead-free (RoHS 6) packaging
• Supports
105°C
board temperature operations
Block Diagram
Q0
Pulldown
Pin Assignments
nCLK1
GNDO
Q1
Q2
SEL[1: 0]
32
31
30
29
28
27
26
CLK0
nCLK0
Pulldown
Pullup Pulldown
/
00
Q0
Q3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
GNDO
25
24
23
22
CLK1
SEL0
SEL1
GND
OE
Q9
V
DDO
Q8
GNDO
Q7
V
DDO
Q6
V
DDO
Q4
CLK1
nCLK1
Pulldown
Pullup/Pulldown
01
Q5
Q1
GNDO
Q2
V
DDO
Q3
Q4
XTAL_OUT
XTAL_IN
OSC
1x
Q6
8L30110
21
20
19
18
17
Q7
Q8
Q9
Q5
GNDO
XTAL_OUT
XTAL_IN
nCLK0
OE
SYNC
32-pin, 5mm x 5mm VFQFN Package
©2017 Integrated Device Technology, Inc.
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September 10, 2017
GNDO
V
DD
CLK0
GND
Pulldown
8L30110 Datasheet
Pin Characteristics
Table 1. Pin Descriptions
[a]
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
ePad
Name
Q0
V
DDO
Q1
GNDO
Q2
V
DDO
Q3
Q4
GNDO
V
DD
XTAL_IN
XTAL_OUT
CLK0
nCLK0
GND
GNDO
Q5
Q6
V
DDO
Q7
GNDO
Q8
V
DDO
Q9
GNDO
GND
nCLK1
CLK1
SEL1
SEL0
OE
GNDO
GND_EP
Output
Power
Output
Power
Output
Power
Output
Output
Power
Power
Input
Output
Input
Input
Power
Power
Output
Output
Power
Output
Power
Output
Power
Output
Power
Power
Input
Input
Input
Input
Input
Power
Power
Pullup/
Pulldown
Pulldown
Pulldown
Pulldown
Pulldown
Pulldown
Pullup/
Pulldown
Type
Description
Single-ended clock outputs. LVCMOS/LVTTL interface levels.
Output supply.
Single-ended clock outputs. LVCMOS/LVTTL interface levels.
Power supply output ground.
Single-ended clock outputs. LVCMOS/LVTTL interface levels.
Output supply.
Single-ended clock outputs. LVCMOS/LVTTL interface levels.
Single-ended clock outputs. LVCMOS/LVTTL interface levels.
Power supply output ground.
Power supply.
Crystal input.
Crystal output.
Non-inverting differential clock.
Inverting differential clock. Internal resistor bias to V
DD
/2.
Power supply core ground.
Power supply output ground.
Single-ended clock outputs. LVCMOS/LVTTL interface levels.
Single-ended clock outputs. LVCMOS/LVTTL interface levels.
Output supply.
Single-ended clock outputs. LVCMOS/LVTTL interface levels.
Power supply output ground.
Single-ended clock outputs. LVCMOS/LVTTL interface levels.
Output supply.
Single-ended clock outputs. LVCMOS/LVTTL interface levels.
Power supply output ground.
Power supply core ground.
Inverting differential clock. Internal resistor bias to V
DD
/2.
Non-inverting differential clock.
Input clock selection. LVCMOS/LVTTL interface levels.
See Table 3A.
Input clock selection. LVCMOS/LVTTL interface levels.
See Table 3A.
Output enable. LVCMOS/LVTTL interface levels. See Table
3B.
Power supply output ground.
Exposed pad of package. Connect to ground.
[a]
Pullup
and
Pulldown
refer to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
©2017 Integrated Device Technology, Inc.
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September 10, 2017
8L30110 Datasheet
Table 2. Pin Characteristics
[a]
Symbol
C
IN
R
PULLDOWN
R
PULLUP
Parameter
Input
Capacitance
SEL[1:0], OE
CLK0, nCLK0,
CLK1, nCLK1
Test Conditions
Minimum
Typical
2
51
51
V
DDO
= 3.465V, f = 100MHz
C
PD
Power Dissipation Capacitance
(per output)
V
DDO
= 2.625V, f = 100MHz
V
DDO
= 2V, f = 100MHz
V
DDO
= 1.65V, f = 100MHz
V
DDO
= 3.3V
R
OUT
Output Impedance
V
DDO
= 2.5V
V
DDO
= 1.8V
V
DDO
= 1.5V
15
18
25
30
9.5
7.4
7.2
6.9
Maximum
Units
pF
k
k
pF
pF
pF
pF
Input Pulldown Resistor
Input Pullup Resistor
[a] Measured at ambient temperature (unless otherwise noted.)
Function Tables
Table 3A. SELx Function Table
Control Input
SEL[1:0]
00 (default)
01
11 or 10
Selected Input Clock
CLK0, nCLK0
CLK1, nCLK1
XTAL
Table 3B. OE Function Table
Control Input
OE
0 (default)
1
Function
Q[0:9]
High-Impedance
Enabled
Table 3C. Input/Output Operation Table
[a]
Input State
CLK0, CLK1 = HIGH
nCLK0, nCLK1 = LOW
CLK0, CLK1 = LOW
nCLK0, nCLK1 = HIGH
CLK0, nCLK0, CLK1, nCLK1 open
Output State
Logic HIGH
Logic LOW
Logic LOW
[a] Device must have switching edge to obtain output states.
©2017 Integrated Device Technology, Inc.
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September 10, 2017
8L30110 Datasheet
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. These ratings are
stress specifications only. Functional operation of the product at these conditions or any conditions beyond those listed in the
DC
Characteristics or AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
product reliability.
Item
Supply Voltage, V
DD
/V
DDO
Inputs, V
I
CLK
X,
nCLK
X,
XTAL_IN
Other Inputs
Outputs, V
O
T
J
(Junction Temperature)
Storage Temperature, T
STG
Rating
3.6V
3.6V
2V
3.6V
3.6V
125°C
-65°C to 150°C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics,
V
DD
= 3.3V±5%, V
DDO
= 3.3V±5% or 2.5V±5% or 1.8V±0.2V or 1.5V±0.15V, T
A
= -40°C to 85°C,
T
B
= -40°C to 105°C
Symbol
V
DD
Parameter
Power Supply Voltage
Test Conditions
Minimum
3.135
3.135
V
DDO
Output Supply Voltage
2.375
1.6
1.35
I
DD
Static Supply Current
SEL[1:0] = 00 or 01, Outputs Unloaded
SEL[1:0] = 10 or 11, Outputs Unloaded
Typical
3.3
3.3
2.5
1.8
1.5
19
18
Maximum
3.465
3.465
2.625
2
1.65
22
22
Units
V
V
V
V
V
mA
mA
Table 4B. Power Supply DC Characteristics,
V
DD
= 2.5V±5%, V
DDO
= 2.5V±5% or 1.8V±0.2V or 1.5V±0.15V,T
A
= -40°C to 85°C,
T
B
= -40°C to 105°C
Symbol
V
DD
V
DDO
Parameter
Power Supply Voltage
Test Conditions
Minimum
2.375
2.375
Output Supply Current
1.6
1.35
I
DD
Static Supply Current
SEL[1:0] = 00 or 01, Outputs Unloaded
SEL[1:0] = 10 or 11, Outputs Unloaded
Typical
2.5
2.5
1.8
1.5
18
17
Maximum
2.625
2.625
2
1.65
22
22
Units
V
V
V
V
mA
mA
©2017 Integrated Device Technology, Inc.
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8L30110 Datasheet
Table 4C. LVCMOS/LVTTL DC Characteristics,
V
DD
= 3.3V±5% or 2.5V±5%, V
DDO (
V
DD)
= 3.3V±5% or 2.5V±5% or 1.8V±0.2V or 1.5V±0.15V, T
A
= -40°C to 85°C,
T
B
= -40°C to 105°C
Symbol
V
IH
V
IL
I
IH
I
IL
Parameter
Input High Voltage
Test Conditions
V
DD
= 3.3V±5%
V
DD
= 2.5V±5%
V
DD
= 3.3V±5%
V
DD
= 2.5V±5%
V
DD
= V
IN
= 3.465V
V
DD
= 3.465V, V
IN
= 0V
V
DDO
= 3.3V±5%, I
OH
= -12mA
V
DDO
= 2.5V±5%, I
OH
= -8mA
V
DDO
= 1.8V±0.2V, I
OH
= -2mA
V
DDO
= 1.5V±0.15V, I
OH
= -2mA
V
DDO
= 3.3V±5%, I
OL
= 12mA
V
OL
Output Low Voltage
V
DDO
= 2.5V±5%, I
OL
= 8mA
V
DDO
= 1.8V±0.2V, I
OL
= 2mA
V
DDO
= 1.5V±0.15V, I
OL
= 2mA
-5
2.6
1.8
1.2
0.95
0.5
0.5
0.4
0.35
Minimum
2
1.7
-0.3
-0.3
Typical
Maximum
V
DD
+0.3
V
DD
+0.3
0.8
0.7
150
Units
V
V
V
V
µA
µA
V
V
V
V
V
V
V
V
Input Low Voltage
Input High
Current
Input Low
Current
OE, SEL[1:0]
OE, SEL[1:0]
Output High Voltage
V
OH
Table 4D. Differential DC Characteristics,
V
DD
= 3.3V±5% or 2.5V±5%, V
DDO (
V
DD)
= 3.3V±5% or 2.5V±5% or 1.8V±0.2V or 1.5V±0.15V, T
A
= -40°C to 85°C,
T
B
= -40°C to 105°C
Symbol
I
IH
I
IL
V
PP
V
CMR
Parameter
Input High
Current
Input Low
Current
CLK[0:1],
nCLK[0:1]
CLK[0:1]
nCLK[0:1]
Test Conditions
V
DD
= V
IN
= 3.465V or 2.625V
V
DD
= 3.465V or 2.625V, V
IN
= 0V
V
DD
= 3.465V or 2.625V,V
IN
= 0V
-5
-150
0.15
0.5
1.3
V
DD
– 0.85
Minimum
Typical
Maximum
150
Units
µA
µA
µA
V
V
Peak-to-Peak Input Voltage
[a]
Common Mode Input Voltage
[a], [b]
[a] V
IL
should not be less than -0.3V and V
IH
should not be greater than V
DD.
[b] Common mode voltage is defined at the crosspoint.
©2017 Integrated Device Technology, Inc.
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September 10, 2017
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