CAV93C76
EEPROM Serial 8-Kb
Microwire - Automotive
Grade
Description
The CAV93C76 is an Automotive Grade, 8−Kb Microwire Serial
EEPROM memory device, which is configured as either registers of
16 bits (ORG pin at V
CC
or Not Connected) or 8 bits (ORG pin at
GND). Each register can be written (or read) serially by using the DI
(or DO) pin. The CAV93C76 is manufactured using ON
Semiconductor ’s advanced CMOS EEPROM floating gate
technology. The device is designed to endure 1,000,000 program/erase
cycles and has a data retention of 100 years. The device is available in
8−pin SOIC and TSSOP packages.
Features
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SOIC−8
V SUFFIX
CASE 751BD
TSSOP−8
Y SUFFIX
CASE 948AL
PIN CONFIGURATION
CS
SK
DI
DO
1
V
CC
NC
ORG
GND
•
•
•
•
•
•
•
•
•
•
•
•
•
Automotive Temperature Grade 1 (−40°C to +125°C)
High Speed Operation: 2 MHz
2.5 V to 5.5 V Supply Voltage Range
Selectable x8 or x16 Memory Organization
Self−timed Write Cycle with Auto−clear
Software Write Protection
Power−up Inadvertant Write Protection
Low Power CMOS Technology
1,000,000 Program/Erase Cycles
100 Year Data Retention
Sequential Read
8−pin SOIC and TSSOP Packages
This Device is Pb−Free, Halogen Free/BFR Free and RoHS
Compliant
†
V
CC
ORG
CS
SK
GND
CAV93C76
DI
DO
SOIC (V), TSSOP (Y)
(Top View)
PIN FUNCTION
Pin Name
CS
SK
DI
DO
V
CC
GND
ORG
NC
Function
Chip Select
Serial Clock Input
Serial Data Input
Serial Data Output
Power Supply
Ground
Memory Organization
No Connection
NOTE:
When the ORG pin is connected to V
CC
, the
x16 organization is selected. When it is connected to
ground, the x8 organization is selected. If the ORG pin
is left unconnected, then an internal pull−up device will
select the x16 organization.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
Figure 1. Functional Symbol
†For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
©
Semiconductor Components Industries, LLC, 2013
May, 2018
−
Rev. 1
1
Publication Order Number:
CAV93C76/D
CAV93C76
Table 1. ABSOLUTE MAXIMUM RATINGS
Parameters
Storage Temperature
Voltage on any Pin with Respect to Ground (Note 1)
Ratings
−65
to +150
−0.5
to +6.5
Units
°C
V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. The minimum DC input voltage is
−0.5
V. During transitions, inputs may undershoot to
−2.0
V for periods of less than 20 ns. Maximum DC
voltage on output pins is V
CC
+0.5 V, which may overshoot to V
CC
+2.0 V for periods of less than 20 ns.
Table 2. RELIABILITY CHARACTERISTICS
(Note 2)
Symbol
N
END
(Note 3)
T
DR
Endurance
Data Retention
Parameter
Min
1,000,000
100
Units
Program / Erase Cycles
Years
2. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
3. Block Mode, V
CC
= 5 V, 25°C
Table 3. D.C. OPERATING CHARACTERISTICS
Symbol
I
CC1
I
CC2
I
SB1
I
SB2
Parameter
Supply Current (Write)
Supply Current (Read)
Standby Current
(x8 Mode)
Standby Current
(x16 Mode)
Input Leakage Current
Output Leakage
Current
Input Low Voltage
Input High Voltage
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Output Low Voltage
Output High Voltage
(V
CC
= +2.5 V to +5.5 V, T
A
=
−40°C
to +125°C, unless otherwise specified.)
Test Conditions
Write, V
CC
= 5.0 V
Read, DO open, f
SK
= 2 MHz, V
CC
= 5.0 V
V
IN
= GND or V
CC
CS = GND, ORG = GND
V
IN
= GND or V
CC
CS = GND,
ORG = Float or V
CC
V
IN
= GND to V
CC
V
OUT
= GND to V
CC
CS = GND
4.5 V
≤
V
CC
< 5.5 V
4.5 V
≤
V
CC
< 5.5 V
2.5 V
≤
V
CC
< 4.5 V
2.5 V
≤
V
CC
< 4.5 V
4.5 V
≤
V
CC
< 5.5 V, I
OL
= 3 mA
4.5 V
≤
V
CC
< 5.5 V, I
OH
=
−400
mA
2.5 V
≤
V
CC
< 4.5 V, I
OL
= 1 mA
2.5 V
≤
V
CC
< 4.5 V, I
OH
=
−100
mA
V
CC
−
0.2
2.4
0.2
−0.1
2
0
V
CC
x 0.7
Min
Max
2
500
5
3
Units
mA
mA
mA
mA
I
LI
I
LO
V
IL1
V
IH1
V
IL2
V
IH2
V
OL1
V
OH1
V
OL2
V
OH2
2
2
0.8
V
CC
+ 1
V
CC
x 0.2
V
CC
+ 1
0.4
mA
mA
V
V
V
V
V
V
V
V
Table 4. PIN CAPACITANCE
(Note 4)
Symbol
C
OUT
C
IN
Test
Output Capacitance (DO)
Input Capacitance (CS, SK, DI, ORG)
Conditions
V
OUT
= 0 V
V
IN
= 0 V
Min
Typ
Max
5
5
Units
pF
pF
4. These parameters are tested initially and after a design or process change that affects the parameter.
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CAV93C76
Table 5. POWER−UP TIMING
(Notes 6, 5)
Symbol
t
PUR
t
PUW
Power−up to Read Operation
Power−up to Write Operation
Parameter
Max
1
1
Units
ms
ms
5. t
PUR
and t
PUW
are the delays required from the time V
CC
is stable until the specified operation can be initiated.
Table 6. A.C. TEST CONDITIONS
Input Rise and Fall Times
Input Pulse Voltages
Timing Reference Voltages
Input Pulse Voltages
Timing Reference Voltages
Output Load
≤
50 ns
0.4 V to 2.4 V
0.8 V, 2.0 V
0.2 V
CC
to 0.7 V
CC
0.5 V
CC
4.5 V
v
V
CC
v
5.5 V
4.5 V
v
V
CC
v
5.5 V
2.5 V
v
V
CC
v
4.5 V
2.5 V
v
V
CC
v
4.5 V
Current Source I
OLmax
/I
OHmax
; CL = 100 pF
Table 7. A.C. CHARACTERISTICS
Symbol
t
CSS
t
CSH
t
DIS
t
DIH
t
PD1
t
PD0
t
HZ
(Note 6)
t
EW
t
CSMIN
t
SKHI
t
SKLOW
t
SV
SK
MAX
CS Setup Time
CS Hold Time
DI Setup Time
DI Hold Time
Output Delay to 1
Output Delay to 0
(V
CC
= +2.5 V to +5.5 V, T
A
=
−40°C
to +125°C, unless otherwise specified.)
Parameter
Min
50
0
100
100
0.25
0.25
100
5
0.25
0.25
0.25
0.25
DC
2000
Max
Units
ns
ns
ns
ns
ms
ms
ns
ms
ms
ms
ms
ms
kHz
Output Delay to High−Z
Program/Erase Pulse Width
Minimum CS Low Time
Minimum SK High Time
Minimum SK Low Time
Output Delay to Status Valid
Maximum Clock Frequency
6. This parameter is tested initially and after a design or process change that affects the parameter.
Table 8. INSTRUCTION SET
(Note 7)
Instruction
READ
ERASE
WRITE
EWEN
EWDS
ERAL
WRAL
Start
Bit
1
1
1
1
1
1
1
Address
Opcode
10
11
01
00
00
00
00
x8
A10−A0
A10−A0
A10−A0
11XXXXXXXXX
00XXXXXXXXX
10XXXXXXXXX
01XXXXXXXXX
x16
A9−A0
A9−A0
A9−A0
11XXXXXXXX
00XXXXXXXX
10XXXXXXXX
01XXXXXXXX
D7−D0
D15−D0
D7−D0
D15−D0
x8
Data
x16
Comments
Read Address AN– A0
Clear Address AN– A0
Write Address AN– A0
Write Enable
Write Disable
Clear All Addresses
Write All Addresses
7. Address bit A10 for the 1,024x8 org. and A9 for the 512x16 org. are “don’t care” bits, but must be kept at either a “1” or “0” for READ, WRITE
and ERASE commands.
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CAV93C76
Device Operation
The CAV93C76 is a 8192−bit nonvolatile memory
intended for use with industry standard microprocessors.
The CAV93C76 can be organized as either registers of 16
bits or 8 bits. When organized as X16, seven 13−bit
instructions control the read, write and erase operations of
the device. When organized as X8, seven 14−bit instructions
control the read, write and erase operations of the device.
The CAV93C76 operates on a single power supply and will
generate on chip, the high voltage required during any write
operation.
Instructions, addresses, and write data are clocked into the
DI pin on the rising edge of the clock (SK). The DO pin is
normally in a high impedance state except when reading data
from the device, or when checking the ready/busy status
after a write operation.
The ready/busy status can be determined after the start of
a write operation by selecting the device (CS high) and
polling the DO pin; DO low indicates that the write
operation is not completed, while DO high indicates that the
device is ready for the next instruction. If necessary, the DO
pin may be placed back into a high impedance state during
chip select by shifting a dummy “1” into the DI pin. The DO
pin will enter the high impedance state on the falling edge of
the clock (SK). Placing the DO pin into the high impedance
state is recommended in applications where the DI pin and
the DO pin are to be tied together to form a common DI/O
pin.
The format for all instructions sent to the device is a
logical “1” start bit, a 2−bit (or 4−bit) opcode, 10−bit address
(an additional bit when organized X8) and for write
operations a 16−bit data field (8−bit for X8 organizations).
The most significant bit of the address is “don’t care” but it
must be present.
t
SKHI
SK
t
DIS
DI
t
CSS
CS
t
DIS
DO
t
PD0
, t
PD1
DATA VALID
t
CSMN
VALID
VALID
t
DIH
Read
Upon receiving a READ command and an address
(clocked into the DI pin), the DO pin of the CAV93C76 will
come out of the high impedance state and, after sending an
initial dummy zero bit, will begin shifting out the data
addressed (MSB first). The output data bits will toggle on
the rising edge of the SK clock and are stable after the
specified time delay (t
PD0
or t
PD1
).
For the CAV93C76, after the initial data word has been
shifted out and CS remains asserted with the SK clock
continuing to toggle, the device will automatically
increment to the next address and shift out the next data word
in a sequential READ mode. As long as CS is continuously
asserted and SK continues to toggle, the device will keep
incrementing to the next address automatically until it
reaches the end of the address space, then loops back to
address 0. In the sequential READ mode, only the initial data
word is preceeded by a dummy zero bit. All subsequent data
words will follow without a dummy zero bit.
Write
After receiving a WRITE command, address and the data,
the CS (Chip Select) pin must be deselected for a minimum
of t
CSMIN
. The falling edge of CS will start the self clocking
clear and data store cycle of the memory location specified
in the instruction. The clocking of the SK pin is not
necessary after the device has entered the self clocking
mode. The ready/busy status of the CAV93C76 can be
determined by selecting the device and polling the DO pin.
Since this device features Auto−Clear before write, it is
NOT necessary to erase a memory location before it is
written into.
t
SKLOW
t
CSH
Figure 2. Synchronous Data Timing
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CAV93C76
SK
CS
A
N
DI
1
1
0
A
N−1
A
0
Don’t Care
DO
HIGH−Z
Dummy 0
D
15
. . . D
0
or
D
7
. . . D
0
Address + 1
D
15
. . . D
0
or
D
7
. . . D
0
Address + 2
D
15
. . . D
0
or
D
7
. . . D
0
Address + n
D
15
. . .
or
D
7
. . .
Figure 3. READ Instruction Timing
SK
t
CSMIN
CS
A
N
DI
1
0
1
t
SV
DO
HIGH−Z
t
EW
BUSY
READY
t
HZ
HIGH−Z
A
N−1
A
0
D
N
D
0
STATUS
VERIFY
STANDBY
Figure 4. WRITE Instruction Timing
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