FemtoClock™ Crystal-to-LVDS/LVCMOS
Frequency
8402015
DATA SHEET
General Description
8402015 is a low phase noise Clock Synthesizer and is a member of
the high performance clock solutions from IDT. The device provides
three banks of outputs and a reference clock. Each bank can be
enabled by using output enable pins. A 25MHz or 50MHz, 18pF
parallel resonant crystal is used to generate 25MHz LVCMOS,
125MHz LVCMOS and 125MHz LVDS outputs. 8402015 is
packaged in a small, 32-pin VFQFN package that is optimum for
applications with space limitations.
Features
•
Three banks of outputs:
Bank A: three single-ended LVCMOS/LVTTL outputs at 25MHz
or 50MHz
Bank B: three single-ended LVCMOS/LVTTL outputs at 125MHz
Bank C: three differential LVDS outputs at 125MHz
Reference LVCMOS/LVTTL output at 25MHz
•
•
•
•
•
•
•
Crystal input frequency: 25MHz
Maximum output frequency: 125MHz
RMS phase jitter @ 125MHz, using a 25MHz crystal
(637kHz - 62.5MHz): 0.373ps (typical) LVDS output
RMS phase jitter @ 25MHz, using a 25MHz crystal
(12kHz - 1MHz): 0.64ps (typical) LVCMOS output
Full 3.3V supply mode
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) package
Pin Assignment
XTAL_OUT
XTAL_IN
GND
GND
OE1
OE0
OE2
V
DDA
32 31 30 29 28 27 26 25
V
DDO_REF
REF_OUT
GND
GND
QA0
QA1
QA2
V
DDO_A
1
2
3
4
5
6
7
8
9
V
DDO_B
24
23
22
21
20
19
18
17
10 11 12 13 14 15 16
GND
GND
MR
QB0
QB1
QB2
V
DD
V
DDO_C
nQC2
QC2
nC1
QC1
nQC0
QC0
V
DDO_C
8402015
32-Lead VFQFN
5mm x 5mm x 0.925mm package body
K Package
Top View
8402015 Rev B 7/2/15
1
©2015 Integrated Device Technology, Inc.
8402015 DATA SHEET
Block Diagram
OE1 = Pullup
OE[2:0]
OE0, OE2 = Pulldown
3
OE
LOGIC
LVCMOS - 25MHz or
50MHz
QA0
QA1
QA2
÷10
÷20
25MHz
XTAL_IN
LVCMOS - 125MHz
OSC
XTAL_OUT
Phase
Detector
VCO
500MHz
QB0
QB1
QB2
÷4
÷20
LVDS - 125MHz
QC0
nQC0
÷4
QC1
nQC1
QC2
nQC2
MR
Pulldown
LVCMOS - 25MHz
REF_OUT
FEMTOCLOCK™ CRYSTAL-TO-LVDS/LVCMOS FREQUENCY
2
Rev B 7/2/15
8402015 DATA SHEET
Table 1. Pin Descriptions
Number
1
2
3, 4, 13, 16,
25, 32
5, 6, 7
8
9
10, 11, 12
14
15
17, 24
18, 19
20, 21
22, 23
26
27, 29
28
30, 31
Name
V
DDO_REF
REF_OUT
GND
QA0, QA1, QA2
V
DDO_A
V
DDO_B
QB0, QB1, QB2
MR
V
DD
V
DDO_C
QC0, nQC0
QC1, nQC1
QC2, nQC2
V
DDA
OE0, OE2
OE1
XTAL_IN,
XTAL_OUT
Power
Output
Power
Output
Power
Power
Output
Input
Power
Power
Output
Output
Output
Power
Input
Input
Input
Pulldown
Pullup
Pulldown
Type
Description
Output supply pin for REF_OUT output.
Reference clock output. LVCMOS/LVTTL interface levels.
Power supply ground.
Single-ended Bank A clock outputs.LVCMOS/LVTTL interface levels.
Power output supply pin for Bank A LVCMOS outputs.
Power output supply pin for Bank B LVCMOS outputs.
Single-ended Bank B clock outputs.LVCMOS/LVTTL interface levels.
Master reset, resets the internal dividers. During reset, LVCMOS outputs are pulled
LOW, and LVDS outputs are pulled LOW and HIGH (QCx pulled LOW, nQCx
pulled HIGH). LVCMOS/LVTTL interface levels.
Core supply pin.
Power output supply pin for Bank C LVDS outputs.
Differential Bank C clock outputs. LVDS interface levels.
Differential Bank C clock outputs. LVDS interface levels.
Differential Bank C clock outputs. LVDS interface levels.
Analog supply pin.
Output enable and configuration pins. See Table 3.
LVCMOS/LVTTL interface levels.
Output enable and configuration pin. See Table 3.
LVCMOS/LVTTL interface levels.
Crystal oscillator interface. XTAL_OUT is the output, XTAL_IN is the input.
NOTE:
Pullup and Pulldown
refer to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
C
PD
R
PULLUP
R
PULLDOWN
R
OUT
Parameter
Input Capacitance
Power Dissipation
Capacitance (per output)
Input Pullup Resistor
Input Pulldown Resistor
Output
Impedance
QA[0:2],
QB[0:2],
REF_OUT
V
DD
, V
DDO_A,
V
DDO_B,
V
DDO_C
= 3.465V
Test Conditions
Minimum
Typical
4
15
51
51
20
Maximum
Units
pF
pF
k
k
Rev B 7/2/15
3
FEMTOCLOCK™ CRYSTAL-TO-LVDS/LVCMOS FREQUENCY
8402015 DATA SHEET
Function Table
Table 3. OE Function and ConfigurationTable
Inputs
Bank A
OE2
0
0
0*
0
1
1
1
1
*Default
OE1
0
0
1*
1
0
0
1
1
OE0
0
1
0*
1
0
1
0
1
A0
25
25
25
25
50
25
50
Hi-Z
A1
Hi-Z
Hi-Z
25
25
Hi-Z
25
50
Hi-Z
A2
Hi-Z
Hi-Z
Hi-Z
25
Hi-Z
Hi-Z
Hi-Z
Hi-Z
B0
Hi-Z
125
Hi-Z
125
Hi-Z
125
Hi-Z
Hi-Z
Output Frequency (MHz)
Bank B
B1
Hi-Z
Hi-Z
Hi-Z
125
Hi-Z
125
Hi-Z
Hi-Z
B2
Hi-Z
Hi-Z
Hi-Z
125
Hi-Z
Hi-Z
Hi-Z
Hi-Z
C0
125
125
125
125
125
125
125
Hi-Z
Bank C
C1
Hi-Z
Hi-Z
125
125
Hi-Z
125
125
Hi-Z
C2
Hi-Z
Hi-Z
Hi-Z
125
Hi-Z
Hi-Z
Hi-Z
Hi-Z
FEMTOCLOCK™ CRYSTAL-TO-LVDS/LVCMOS FREQUENCY
4
Rev B 7/2/15
8402015 DATA SHEET
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics or AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Supply Voltage, V
DD
Inputs, V
I
Outputs, I
O
(LVCMOS)
Outputs, I
O
(LVDS)
Continuos Current
Surge Current
Operating Temperature Range, T
A
Package Thermal Impedance,
JA
Storage Temperature, T
STG
Rating
4.6V
-0.5V to V
DD
+ 0.5V
-0.5V to V
DDO_LVCMOS
+ 0.5V
10mA
15mA
-40C to +85C
37C/W (0 mps)
-65C to 150C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics,
V
DD
= V
DDO_A
= V
DDO_B
= V
DDO_C
= V
DDO_REF
= 3.3V±5%, T
A
= -40°C to 85°C
Symbol
V
DD
V
DDA
Parameter
Core Supply Voltage
Analog Supply Voltage
Test Conditions
Minimum
3.135
V
DD
– 0.36
Typical
3.3
3.3
Maximum
3.465
V
DD
Units
V
V
V
DDO_A,
V
DDO_B,
Output Supply Voltage
V
DDO_C,
V
DDO_REF
I
DD
I
DDA
I
DDO_A,
I
DDO_B,
I
DDO_C,
I
DDO_REF
Power Supply Current
Analog Supply Current
3.135
3.3
3.465
V
30
36
mA
mA
Total Output Supply Current
Outputs Unused
26
mA
Rev B 7/2/15
5
FEMTOCLOCK™ CRYSTAL-TO-LVDS/LVCMOS FREQUENCY
51单片机
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