CY22393/CY223931
CY22394
CY22395
Three-PLL Serial-Programmable
Flash-Programmable Clock Generator
Three-PLL Serial-Programmable Flash-Programmable Clock Generator
Features
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Advanced Features
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Three integrated phase-locked loops (PLLs)
Ultra wide divide counters (8-bit Q, 11-bit P, and 7-bit post
divide)
Improved linear crystal load capacitors
Flash programmability with external programmer
Field-programmable
Low jitter, high accuracy outputs
Power management options (Shutdown, OE, Suspend)
Configurable crystal drive strength
Frequency select through three external LVTTL inputs
3.3 V operation
16-pin TSSOP package
CyClocksRT™ software support
Two-wire serial interface for in-system configurability
Configurable output buffer
Digital VCXO
High frequency LVPECL output (CY22394 only)
3.3/2.5 V outputs (CY22395 only)
NiPdAu lead finish (CY223931)
Functional Description
The CY22393, CY22394, and CY22395 are a family of parts
designed as upgrades to the existing CY22392 device. These
parts have similar performance to the CY22392, but provide
advanced features to meet the needs of more demanding
applications.
The clock family has three PLLs which, when combined with the
reference, allow up to four independent frequencies to be output
on up to six pins. These three PLLs are completely
programmable.
The CY223931 is the CY22393 with NiPdAu lead finish.
For a complete list of related documentation, click
here.
Selector Guide
Part Number
CY22393_C
CY22393_I
CY223931_I
CY22394_C
CY22394_I
CY22395_C
CY22395_I
Outputs
6 CMOS
6 CMOS
6 CMOS
1 PECL/
4 CMOS
1 PECL/
4 CMOS
Input Frequency Range
8 MHz–30 MHz (external crystal)
1 MHz–166 MHz (reference clock)
8 MHz–30 MHz (external crystal)
1 MHz–166 MHz (reference clock)
8 MHz–30 MHz (external crystal)
1 MHz–166 MHz (reference clock)
8 MHz–30 MHz (external crystal)
1 MHz–166 MHz (reference clock)
8 MHz–30 MHz (external crystal)
1 MHz–150 MHz (reference clock)
Output Frequency Range
Up to 200 MHz
Up to 166 MHz
Up to 166 MHz
100 MHz–400 MHz (PECL)
Up to 200 MHz (CMOS)
125 MHz–375 MHz (PECL)
Up to 166 MHz (CMOS)
Up to 200 MHz (3.3 V)
Up to 133 MHz (2.5 V)
Up to 166 MHz (3.3 V)
Up to 133 MHz (2.5 V)
Specifics
Commercial temperature
Industrial temperature
Industrial temperature
Commercial temperature
Industrial temperature
Commercial temperature
Industrial temperature
4 LVCMOS/ 1 8 MHz–30 MHz (external crystal)
CMOS
1 MHz–166 MHz (reference clock)
4 LVCMOS/ 1 8 MHz–30 MHz (external crystal)
CMOS
1 MHz–150 MHz (reference clock)
Cypress Semiconductor Corporation
Document Number: 38-07186 Rev. *M
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised May 11, 2017
CY22393/CY223931
CY22394
CY22395
Contents
Pinouts .............................................................................. 5
Pin Definitions .................................................................. 5
Functional Overview ........................................................ 6
Configurable PLLs ....................................................... 6
General Purpose Inputs .............................................. 6
Crystal Input ................................................................ 6
Crystal Drive Level and Power .................................... 6
Digital VCXO ............................................................... 6
Output Configuration ................................................... 6
Power-Saving Features ............................................... 7
Improving Jitter ............................................................ 7
Power Supply Sequencing .......................................... 7
CyClocksRT Software ...................................................... 7
Junction Temperature Limitations ............................... 7
Dynamic Updates ........................................................ 7
Memory Bitmap Definitions ............................................. 8
Clk{A–D}_Div[6:0] ........................................................ 8
ClkE_Div[1:0] ............................................................... 8
Clk*_FS[2:0] ................................................................ 8
Xbuf_OE ...................................................................... 8
PdnEn .......................................................................... 8
Clk*_ACAdj[1:0] ........................................................... 8
Clk*_DCAdj[1:0] .......................................................... 8
PLL*_Q[7:0] ................................................................. 8
PLL*_P[9:0] ................................................................. 8
PLL*_P ........................................................................ 8
PLL*_LF[2:0] ............................................................... 9
PLL*_En ...................................................................... 9
DivSel .......................................................................... 9
OscCap[5:0] ................................................................ 9
OscDrv[1:0] ................................................................. 9
Reserved ..................................................................... 9
Serial Programming Bitmaps — Summary Tables ...... 10
Serial Bus Programming Protocol and Timing ............ 11
Default Startup Condition
for the CY22393/931/94/95 .............................................. 11
Device Address ......................................................... 11
Data Valid .................................................................. 11
Data Frame ............................................................... 11
Acknowledge Pulse ................................................... 11
Write Operations ............................................................. 12
Writing Individual Bytes ............................................. 12
Writing Multiple Bytes ................................................ 12
Read Operations ............................................................. 12
Current Address Read ............................................... 12
Random Read ........................................................... 12
Sequential Read ........................................................ 12
Serial Programming Interface Timing ........................... 14
Serial Programming Interface Timing
Specifications ................................................................. 14
Absolute Maximum Conditions ..................................... 15
Operating Conditions ..................................................... 15
Recommended Crystal Specifications ......................... 15
3.3 V Electrical Characteristics ..................................... 16
2.5 V Electrical Characteristics ..................................... 16
Thermal Resistance ........................................................ 16
3.3 V Switching Characteristics .................................... 17
2.5 V Switching Characteristics .................................... 17
Switching Waveforms .................................................... 18
Test Circuit ...................................................................... 19
Ordering Information ...................................................... 20
Possible Configurations ............................................. 20
Ordering Code Definitions ......................................... 21
Package Diagram ............................................................ 22
Acronyms ........................................................................ 23
Document Conventions ................................................. 23
Units of Measure ....................................................... 23
Document History Page ................................................. 24
Sales, Solutions, and Legal Information ...................... 25
Worldwide Sales and Design Support ....................... 25
Products .................................................................... 25
PSoC®Solutions ....................................................... 25
Cypress Developer Community ................................. 25
Technical Support ..................................................... 25
Document Number: 38-07186 Rev. *M
Page 4 of 25
CY22393/CY223931
CY22394
CY22395
Pinouts
Figure 1. Pin Diagram: 16-pin TSSOP CY22393/CY223931/CY22394/CY22395
1
CY223931
CLKC
V
DD
AGND
XTALIN
XTALOUT
XBUF
CLKD
CLKE
16
2
CY22393
15
3
4
5
6
7
8
14
13
12
11
10
9
SHUTDOW N
/OE
S2/
SUSPEND
AV
D D
SCLK(S1)
SDAT(S0)
GND
CLKA
CLKB
CLKC
V
DD
AGND
XTALIN
1
2
3
4
5
6
7
8
CY22394
16
15
14
13
12
11
10
9
SHUTDOW N
/OE
S2/
SUSPEND
AV
D D
SCLK(S1)
CLKC
V
DD
AGND
XTALIN
1
2
3
4
5
6
7
8
CY22395
16
15
14
13
12
11
10
9
SHUTDOW N
/OE
S2/
SUSPEND
AV
DD
SCLK(S1)
SDAT(S0)
GND/
LGND
LCLKA
LCLKB
XTALOUT
XBUF
P-CLK
P+CLK
SDAT(S0) XTALOUT
GND
CLKA
CLKB
LV
DD
LCLKD
LCLKE
Pin Definitions
Name
CLKC
V
DD
AGND
XTALIN
XTALOUT
XBUF
LV
DD
CLKD or LCLKD
P– CLK
CLKE or LCLKE
P+ CLK
CLKB or LCLKB
CLKA or LCLKA
GND/LGND
SDAT (S0)
SCLK (S1)
AV
DD
S2/
SUSPEND
SHUTDOWN/
OE
Pin Number
CY22393
CY223931
1
2
3
4
5
6
N/A
7
N/A
8
N/A
9
10
11
12
13
14
15
16
Pin Number
CY22394
1
2
3
4
5
6
N/A
N/A
7
N/A
8
9
10
11
12
13
14
15
16
Pin Number
CY22395
1
2
3
4
5
N/A
6
7
N/A
8
N/A
9
10
11
12
13
14
15
16
Power supply
Analog Ground
Reference crystal input or external reference clock input
Reference crystal feedback
Buffered reference clock output
Low voltage clock output power supply
Configurable clock output D; LCLKD referenced to LVDD
LV PECL output
[1]
Configurable clock output E; LCLKE referenced to LVDD
LV PECL output
[1]
Configurable clock output B; LCLKB referenced to LVDD
Configurable clock output A; LCLKA referenced to LVDD
Ground
Serial port data. S0 value latched during start up
Serial port clock. S1 value latched during start up
Analog power supply
General purpose input for frequency control; bit 2. Optionally,
Suspend mode control input
Places outputs in tristate condition and shuts down chip when
LOW. Optionally, only places outputs in tristate condition and
does not shut down chip when LOW
Description
Configurable clock output C
Note
1. LVPECL outputs require an external termination network.
Document Number: 38-07186 Rev. *M
Page 5 of 25
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