GTL2007
12-bit GTL to LVTTL translator with power good control
Rev. 02 — 16 February 2007
Product data sheet
1. General description
The GTL2007 is a customized translator between dual Xeon processors, Platform Health
Management, South Bridge and Power Supply LVTTL and GTL signals.
The GTL2007 is derived from the GTL2006 with an enable function added that disables
the error output to the monitoring agent for platforms that monitor the individual error
conditions from each processor. This enable function can be used so that false error
conditions are not passed to the monitoring agent when the system is unexpectedly
powered down. This unexpected power-down could be from a power supply overload, a
CPU thermal trip, or some other event of which the monitoring agent is unaware.
A typical implementation would be to connect each enable line to the system power good
signal or the individual enables to the VRD power good for each processor.
Typically Xeon processors specify a V
TT
of 1.1 V to 1.2 V, as well as a nominal V
ref
of
0.73 V to 0.76 V. To allow for future voltage level changes that may extend V
ref
to 0.63 of
V
TT
(minimum of 0.693 V with V
TT
of 1.1 V) the GTL2007 allows a minimum V
ref
of 0.66 V.
Characterization results show that there is little DC or AC performance variation between
these V
ref
levels.
2. Features
I
I
I
I
I
I
I
Operates as a GTL to LVTTL sampling receiver or LVTTL to GTL driver
Operates at GTL−/GTL/GTL+ signal levels
EN1 and EN2 disable error output
3.0 V to 3.6 V operation
LVTTL I/O not 5 V tolerant
Series termination on the LVTTL outputs of 30
Ω
ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per
JESD22-A115, and 1000 V CDM per JESD22-C101
I
Latch-up testing is done to JEDEC Standard JESD78 which exceeds 500 mA
I
Package offered: TSSOP28
NXP Semiconductors
GTL2007
12-bit GTL to LVTTL translator with power good control
3. Quick reference data
Table 1.
Quick reference data
T
amb
= 25
°
C.
Symbol
C
io
Parameter
input/output capacitance
Conditions
A port; V
O
= 3.0 V or 0 V
B port; V
O
= V
TT
or 0 V
V
ref
= 0.73 V; V
TT
= 1.1 V
t
PLH
t
PHL
LOW-to-HIGH
propagation delay
HIGH-to-LOW
propagation delay
nA to nB; see
Figure 4
nBI to nAO; see
Figure 5
nA to nB; see
Figure 4
nBI to nAO; see
Figure 5
nA to nB; see
Figure 4
nBI to nAO; see
Figure 5
nA to nB; see
Figure 4
nBI to nAO; see
Figure 5
1
2
2
2
1
2
2
2
4
5.5
5.5
5.5
4
5.5
5.5
5.5
8
10
10
10
8
10
10
10
ns
ns
ns
ns
ns
ns
ns
ns
Min
-
-
Typ
2.5
1.5
Max
3.5
2.5
Unit
pF
pF
V
ref
= 0.76 V; V
TT
= 1.2 V
t
PLH
t
PHL
LOW-to-HIGH
propagation delay
HIGH-to-LOW
propagation delay
4. Ordering information
Table 2.
Ordering information
T
amb
=
−
40
°
C to +85
°
C.
Type number
GTL2007PW
Topside
mark
GTL2007
Package
Name
TSSOP28
Description
plastic thin shrink small outline package;
28 leads; body width 4.4 mm
Version
SOT361-1
GTL2007_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 16 February 2007
2 of 20
NXP Semiconductors
GTL2007
12-bit GTL to LVTTL translator with power good control
5. Functional diagram
GTL2007
GTL VREF
1AO
LVTTL outputs
2AO
3
26
2BI
1
2
27
1BI
GTL inputs
5A
LVTTL inputs/outputs
(open-drain)
6A
4
&
25
7BO1
GTL outputs
5
&
24
7BO2
LVTTL input
EN1
6
23
EN2
LVTTL input
GTL input
11BI
7
1
22
11BO
GTL output
LVTTL input/output
(open-drain)
11A
8
DELAY
(1)
21
5BI
GTL input
9BI
9
DELAY
(1)
20
6BI
GTL inputs
3AO
LVTTL outputs
4AO
10
19
3BI
11
18
4BI
1
10AI1
LVTTL inputs
10AI2
13
12
1
17
10BO1
GTL outputs
16
10BO2
15
9AO
LVTTL output
002aab210
(1) The enable on 7BO1/7BO2 include a delay that prevents the transient condition where 5BI/6BI go from LOW to HIGH, and
the LOW to HIGH on 5A/6A lags up to 100 ns from causing a LOW glitch on the 7BO1/7BO2 outputs.
Fig 1. Logic diagram of GTL2007
GTL2007_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 16 February 2007
3 of 20
NXP Semiconductors
GTL2007
12-bit GTL to LVTTL translator with power good control
6. Pinning information
6.1 Pinning
VREF
1AO
2AO
5A
6A
EN1
11BI
11A
9BI
1
2
3
4
5
6
7
8
9
28 V
CC
27 1BI
26 2BI
25 7BO1
24 7BO2
23 EN2
22 11BO
21 5BI
20 6BI
19 3BI
18 4BI
17 10BO1
16 10BO2
15 9AO
002aab209
GTL2007PW
3AO 10
4AO 11
10AI1 12
10AI2 13
GND 14
Fig 2. Pin configuration for TSSOP28
6.2 Pin description
Table 3.
Symbol
VREF
1AO
2AO
5A
6A
EN1
11BI
11A
9BI
3AO
4AO
10AI1
10AI2
GND
9AO
10BO2
10BO1
4BI
3BI
GTL2007_2
Pin description
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
Description
GTL reference voltage
data output (LVTTL)
data output (LVTTL)
data input/output (LVTTL), open-drain
data input/output (LVTTL), open-drain
enable input (LVTTL)
data input (GTL)
data input/output (LVTTL), open-drain
data input (GTL)
data output (LVTTL)
data output (LVTTL)
data input (LVTTL)
data input (LVTTL)
ground (0 V)
data output (LVTTL)
data output (GTL)
data output (GTL)
data input (GTL)
data input (GTL)
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 16 February 2007
4 of 20
NXP Semiconductors
GTL2007
12-bit GTL to LVTTL translator with power good control
Pin description
…continued
Pin
20
21
22
23
24
25
26
27
28
Description
data input (GTL)
data input (GTL)
data output (GTL)
enable input (LVTTL)
data output (GTL)
data output (GTL)
data input (GTL)
data input (GTL)
positive supply voltage
Table 3.
Symbol
6BI
5BI
11BO
EN2
7BO2
7BO1
2BI
1BI
V
CC
7. Functional description
Refer to
Figure 1 “Logic diagram of GTL2007”.
7.1 Function tables
Table 4.
GTL input signals
H = HIGH voltage level; L = LOW voltage level.
Input
1BI/2BI/3BI/4BI/9BI
L
H
[1]
Output
[1]
1AO/2AO/3AO/4AO/9AO
L
H
1AO, 2AO, 3AO, 4AO and 5A/6A condition changed by ENn power good signal as described in
Table 5
and
Table 6.
Table 5.
EN1 power good signal
H = HIGH voltage level; L = LOW voltage level.
EN1
L
H
1AO and 2AO
H
follows BI
5A
5BI disconnected
5BI connected
Table 6.
EN2 power good signal
H = HIGH voltage level; L = LOW voltage level.
EN2
L
H
3AO and 4AO
H
follows BI
6A
6BI disconnected
6BI connected
GTL2007_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 16 February 2007
5 of 20
嵌入式系统
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