MM74HC74A — Dual D-Type Flip-Flop with Preset and Clear
February 2008
MM74HC74A
Dual D-Type Flip-Flop with Preset and Clear
Features
■
Typical propagation delay: 20ns
■
Wide power supply range: 2V–6V
■
Low quiescent current: 40µA maximum (74HC Series)
■
Low input current: 1µA maximum
■
Fanout of 10 LS-TTL loads
General Description
The MM74HC74A utilizes advanced silicon-gate CMOS
technology to achieve operating speeds similar to the
equivalent LS-TTL part. It possesses the high noise
immunity and low power consumption of standard
CMOS integrated circuits, along with the ability to drive
10 LS-TTL loads.
This flip-flop has independent data, preset, clear, and
clock inputs and Q and Q outputs. The logic level
present at the data input is transferred to the output dur-
ing the positive-going transition of the clock pulse. Pre-
set and clear are independent of the clock and
accomplished by a low level at the appropriate input.
The 74HC logic family is functionally and pinout compat-
ible with the standard 74LS logic family. All inputs are
protected from damage due to static discharge by inter-
nal diode clamps to V
CC
and ground.
Ordering Information
Order Number
MM74HC74AM
MM74HC74ASJ
MM74HC74AMTC
MM74HC74AN
Package
Number
M14A
M14D
MTC14
N14A
Package Description
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150"
Narrow
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153,
4.4mm Wide
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
All packages are lead free per JEDEC: J-STD-020B standard.
©1983 Fairchild Semiconductor Corporation
MM74HC74A Rev. 1.3.0
www.fairchildsemi.com
MM74HC74A — Dual D-Type Flip-Flop with Preset and Clear
Connection Diagram
Pin Assignments for DIP, SOIC, SOP and TSSOP
Truth Table
Inputs
PR
L
H
L
H
H
H
Note:
Q0
=
the level of Q before the indicated input conditions
were established.
1. This configuration is nonstable; that is, it will not persist
when preset and clear inputs return to their inactive
(HIGH) level.
Outputs
D
X
X
X
H
L
X
CLR
H
L
L
H
H
H
CLK
X
X
X
↑
↑
L
Q
H
L
H
(1)
H
L
Q0
Q
L
H
H
(1)
L
H
Q0
Top View
Logic Diagram
©1983 Fairchild Semiconductor Corporation
MM74HC74A Rev. 1.3.0
www.fairchildsemi.com
2
MM74HC74A — Dual D-Type Flip-Flop with Preset and Clear
Absolute Maximum Ratings
(2)
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
V
CC
V
IN
V
OUT
I
IK
, I
OK
I
OUT
I
CC
T
STG
P
D
Supply Voltage
DC Input Voltage
DC Output Voltage
Clamp Diode Current
DC Output Current, per pin
Parameter
Rating
–0.5 to +7.0V
–1.5 to V
CC
+1.5V
–0.5 to V
CC
+0.5V
±20mA
±25mA
±50mA
–65°C to +150°C
600mW
500mW
260°C
DC V
CC
or GND Current, per pin
Storage Temperature Range
Power Dissipation
Note 3
S.O. Package only
Lead Temperature (Soldering 10 seconds)
T
L
Notes:
2. Unless otherwise specified all voltages are referenced to ground.
3. Power Dissipation temperature derating — plastic “N” package: –12mW/°C from 65°C to 85°C.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.
Symbol
V
CC
V
IN
, V
OUT
T
A
t
r
, t
f
Supply Voltage
DC Input or Output Voltage
Parameter
Min.
2
0
–40
Max.
6
V
CC
+85
1000
500
400
Units
V
V
°C
ns
ns
ns
Operating Temperature Range
Input Rise or Fall Times
V
CC
=
2.0V
V
CC
=
4.5V
V
CC
=
6.0V
©1983 Fairchild Semiconductor Corporation
MM74HC74A Rev. 1.3.0
www.fairchildsemi.com
3
MM74HC74A — Dual D-Type Flip-Flop with Preset and Clear
DC Electrical Characteristics
(4)
T
A
=
25°C
Symbol
V
IH
T
A
=
–40°C
to 85°C
1.5
3.15
4.2
0.5
1.35
1.8
1.9
4.4
5.9
3.84
5.34
0.1
0.1
0.1
0.33
0.33
±1.0
40
T
A
=
–55°C
to 125°C
Units
V
1.5
3.15
4.2
0.5
1.35
1.8
1.9
4.4
5.9
3.7
5.2
0.1
0.1
0.1
0.4
0.4
±1.0
80
µA
µA
V
V
V
Parameter
Minimum HIGH
Level Input
Voltage
Maximum LOW
Level Input
Voltage
Minimum HIGH
Level Output
Voltage
V
CC
(V)
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
Conditions
Typ.
1.5
3.15
4.2
0.5
1.35
1.8
Guaranteed Limits
V
IL
V
OH
V
IN
=
V
IH
or V
IL
,
|I
OUT
|
≤
20µA
V
IN
=
V
IH
or V
IL
,
|I
OUT
|
≤
4.0mA
V
IN
=
V
IH
or V
IL
,
|I
OUT
|
≤
5.2mA
V
IN
=
V
IH
or V
IL
,
|I
OUT
|
≤
20µA
V
IN
=
V
IH
or V
IL
,
|I
OUT
|
≤
4.0mA
|V
IN
=
V
IH
or V
IL
,
I
OUT
|
≤
5.2mA
V
IN
=
V
CC
or GND
V
I N
=
V
CC
or GND,
I
OUT
=
0µA
2.0
4.5
6.0
4.3
5.2
0
0
0
0.2
0.2
1.9
4.4
5.9
3.98
5.48
0.1
0.1
0.1
0.26
0.26
±0.1
4.0
V
OL
Maximum LOW
Level Output
Voltage
2.0
4.5
6.0
4.5
6.0
I
IN
I
CC
Maximum Input
Current
Maximum
Quiescent
Supply Current
6.0
6.0
Note:
4. For a power supply of 5V ±10% the worst case output voltages (V
OH
, and V
OL
) occur for HC at 4.5V. Thus the 4.5V
values should be used when designing with this supply. Worst case V
IH
and V
IL
occur at V
CC
=
5.5V and 4.5V
respectively. (The V
IH
value at 5.5V is 3.85V.) The worst case leakage current (I
IN
, I
CC
, and I
OZ
) occur for CMOS at
the higher voltage and so the 6.0V values should be used.
©1983 Fairchild Semiconductor Corporation
MM74HC74A Rev. 1.3.0
www.fairchildsemi.com
4
MM74HC74A — Dual D-Type Flip-Flop with Preset and Clear
AC Electrical Characteristics
V
CC
=
5V, T
A
=
25°C, C
L
=
15pF, t
r
=
t
f
=
6ns
Symbol
f
MAX
t
PHL
, t
PLH
t
PHL
, t
PLH
t
REM
t
s
t
H
t
W
Parameter
Maximum Operating Frequency
Maximum Propagation,
Delay Clock to Q or Q
Maximum Propagation,
Delay Preset or Clear to Q or Q
Minimum Removal Time,
Preset or Clear to Clock
Minimum Setup Time, Data to Clock
Minimum Hold Time, Clock to Data
Minimum Pulse Width Clock, Preset or Clear
Conditions
Typ.
72
10
17
6
10
0
8
Guaranteed
Limit
30
30
40
5
20
0
16
Units
MHz
ns
ns
ns
ns
ns
ns
©1983 Fairchild Semiconductor Corporation
MM74HC74A Rev. 1.3.0
www.fairchildsemi.com
5
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