SiC620R, SiC620AR
www.vishay.com
Vishay Siliconix
60 A VRPower
®
Integrated Power Stage
DESCRIPTION
The SiC620R and SiC620AR are integrated power stage
solutions optimized for synchronous buck applications to
offer high current, high efficiency, and high power density
performance. Packaged in Vishay’s proprietary 5 mm x 5 mm
MLP package, SiC620R and SiC620AR enables voltage
regulator designs to deliver up to 60 A continuous current
per phase.
The internal power MOSFETs utilizes Vishay’s
state-of-the-art Gen IV TrenchFET technology that delivers
industry benchmark performance to significantly reduce
switching and conduction losses.
The SiC620R and SiC620AR incorporates an advanced
MOSFET gate driver IC that features high current driving
capability, adaptive dead-time control, an integrated
bootstrap Schottky diode, a thermal warning (THWn) that
alerts the system of excessive junction temperature, and
zero current detect to improve light load efficiency. The
drivers are also compatible with a wide range of PWM
controllers and supports tri-state PWM, 3.3 V (SiC620AR) /
5 V (SiC620R) PWM logic.
FEATURES
• Thermally enhanced PowerPAK
®
MLP55-31L
double cooling package
• Vishay’s Gen IV MOSFET technology and a
low-side MOSFET with integrated Schottky
diode
• Delivers up to 60 A continuous current
• 95 % peak efficiency
• High frequency operation up to 1.5 MHz
• Power MOSFETs optimized for 12 V input stage
• 3.3 V (SiC620AR) / 5 V (SiC620R) PWM logic with tri-state
and hold-off
• Zero current detect control for light load efficiency
improvement
• Low PWM propagation delay (< 20 ns)
• Thermal monitor flag
• Under voltage lockout for V
CIN
• Material categorization: for definitions of compliance
please see
www.vishay.com/doc?99912
APPLICATIONS
• Multi-phase VRDs for CPU, GPU, and memory
TYPICAL APPLICATION DIAGRAM
5V
V
DRV
V
IN
V
IN
GH
BOOT
V
CIN
ZCD_EN#
PWM
controller
DSBL#
PWM
THWn
Gate
driver
PHASE
V
SWH
V
OUT
Fig. 1 - SiC620R and SiC620AR Typical Application Diagram
C
GND
GL
P
GND
S14-2189, Rev. A 03-Nov-14
Document Number: 63589
1
For technical questions, contact:
powerictechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
SiC620R, SiC620AR
www.vishay.com
PINOUT CONFIGURATION
Vishay Siliconix
31 30 29 28 27 26 25 24
PWM 1
ZCD_EN# 2
V
CIN
3
C
GND
4
BOOT 5
GH
6
PHASE 7
15
33
GL
24 25 26 27 28 29 30 31
1 PWM
GL
23 V
SWH
22 V
SWH
21 V
SWH
20 V
SWH
19 V
SWH
18 V
SWH
17 V
SWH
16 V
SWH
9
V
IN
10 11
V
IN
V
IN
12 13 14 15
P
GND
P
GND
P
GND
P
GND
V
SWH
23
V
SWH
22
V
SWH
21
V
SWH
20
V
SWH
19
V
SWH
18
V
SWH
17
V
SWH
16
35
PGND
DSBL#
THWn
V
SWH
V
SWH
V
SWH
P
GND
V
DRV
GL
DSBL#
THWn
V
SWH
V
SWH
V
SWH
P
GND
V
DRV
GL
32
CGND
2 ZCD_EN#
3 V
CIN
4 C
GND
5 BOOT
6 HG
34
VIN
7 PHASE
8 V
IN
V
IN
8
15 14 13 12
P
GND
P
GND
P
GND
P
GND
11 10
V
IN
V
IN
9
V
IN
Top view
Bottom view
Fig. 2 - SiC620R and SiC620AR Pin Configuration
PIN CONFIGURATION
PIN NUMBER
1
2
3
4, 32
5
6
7
8 to 11, 34
12 to 15, 28, 35
16 to 26
27, 33
29
30
31
NAME
PWM
ZCD_EN#
V
CIN
C
GND
BOOT
GH
PHASE
V
IN
P
GND
V
SWH
GL
V
DRV
THWn
DSBL#
PWM control input
ZCD control. Active low
Supply voltage for internal logic circuitry
Analog ground for the driver IC
High-side driver bootstrap voltage
High-side gate signal
Return path of high-side gate driver
Power stage input voltage. Drain of high-side MOSFET
Power ground
Switch node of the power stage
Low-side gate signal
Supply voltage for internal gate driver
Thermal warning open drain output
Disable pin. Active low
FUNCTION
ORDERING INFORMATION
PART NUMBER
SiC620RCD-T1-GE3
SiC620ARCD-T1-GE3
SiC620RDB / SiC620ARDB
S14-2189, Rev. A 03-Nov-14
PACKAGE
PowerPAK MLP55-31L
PowerPAK MLP55-31L
MARKING CODE
SiC620R
SiC620AR
Reference board
OPTION
5 V PWM optimized
3.3 V PWM optimized
Document Number: 63589
2
For technical questions, contact:
powerictechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
SiC620R, SiC620AR
www.vishay.com
Vishay Siliconix
CONDITIONS
V
IN
V
CIN
V
DRV
LIMIT
-0.3 to +25
-0.3 to +7
-0.3 to +7
-0.3 to +25
-7 to +30
32
38
-0.3 to +7
-0.3 to +8
-0.3 to V
CIN
+0.3
f
S
= 300 kHz, V
IN
= 12 V, V
OUT
= 1.8 V
f
S
= 1 MHz, V
IN
= 12 V, V
OUT
= 1.8 V
T
J
T
A
T
stg
Human body model, JESD22-A114
Charged device model, JESD22-C101
60
50
150
-40 to +125
-65 to +150
3000
500
V
°C
A
V
UNIT
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL PARAMETER
Input Voltage
Control Logic Supply Voltage
Drive Supply Voltage
Switch Node (DC voltage)
Switch Node (AC voltage)
(1)
V
SWH
V
BOOT
V
BOOT-PHASE
BOOT Voltage (DC voltage)
BOOT Voltage (AC voltage)
(2)
BOOT to PHASE (DC voltage)
BOOT to PHASE (AC
voltage)
(3)
All Logic Inputs and Outputs
(PWM, DSBL#, and THWn)
Output Current, I
OUT(AV) (4)
Max. Operating Junction Temperature
Ambient Temperature
Storage Temperature
Electrostatic Discharge Protection
Notes
• Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
(1)
The specification values indicated “AC” is V
SWH
to P
GND
-8 V (< 20 ns, 10 μJ), min. and 30 V (< 50 ns), max.
(2)
The specification value indicates “AC voltage” is V
BOOT
to P
GND
, 38 V (< 50 ns) max.
(3)
The specification value indicates “AC voltage” is V
BOOT
to V
PHASE
, 8 V (< 20 ns) max.
(4)
Output current rated with testing evaluation board at T = 25 °C with natural convection cooling. The rating is limited by the peak evaluation
A
board temperature, T
J
RECOMMENDED OPERATING RANGE
ELECTRICAL PARAMETER
Input Voltage (V
IN
)
Drive Supply Voltage (V
DRV
)
Control Logic Supply Voltage (V
CIN
)
Switch Node (V
SWH
, DC voltage)
BOOT to PHASE (V
BOOT-PHASE
, DC voltage)
Thermal Resistance from Junction to Ambient
Thermal Resistance from Junction to Case
MINIMUM
4.5
4.5
4.5
-
4
-
-
TYPICAL
-
5
5
-
4.5
10.6
1.6
MAXIMUM
18
5.5
5.5
18
5.5
-
-
°C/W
V
UNIT
S14-2189, Rev. A 03-Nov-14
Document Number: 63589
3
For technical questions, contact:
powerictechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
SiC620R, SiC620AR
www.vishay.com
ELECTRICAL SPECIFICATIONS
(DSBL# = ZCD_EN# = 5 V, V
IN
= 12 V, V
DRV
and V
CIN
= 5 V, T
A
= 25 °C)
PARAMETER
POWER SUPPLY
V
DSBL#
= 0 V, no switching
Control Logic Supply Current
I
VCIN
V
DSBL#
= 5 V, no switching, V
PWM
= FLOAT
V
DSBL#
= 5 V, f
S
= 300 kHz, D = 0.1
f
S
= 300 kHz, D = 0.1
Drive Supply Current
I
VDRV
f
S
= 1 MHz, D = 0.1
V
DSBL#
= 0 V, no switching
V
DSBL#
= 5 V, no switching
BOOTSTRAP SUPPLY
Bootstrap Diode Forward Voltage
PWM CONTROL INPUT (SiC620R)
Rising Threshold
Falling Threshold
Tri-state Voltage
Tri-state Rising Threshold
Tri-state Falling Threshold
Tri-state Rising Threshold
Hysteresis
Tri-state Falling Threshold
Hysteresis
PWM Input Current
PWM CONTROL INPUT (SiC620AR)
Rising Threshold
Falling Threshold
Tri-state Voltage
Tri-state Rising Threshold
Tri-state Falling Threshold
Tri-state Rising Threshold
Hysteresis
Tri-state Falling Threshold
Hysteresis
PWM Input Current
TIMING SPECIFICATIONS
Tri-State to GH/GL Rising
Propagation Delay
Tri-state Hold-Off Time
GH - Turn Off Propagation Delay
GH - Turn On Propagation Delay
(Dead time rising)
GL - Turn Off Propagation Delay
GL - Turn On Propagation Delay
(Dead time falling)
DSBL# Lo to GH/GL Falling
Propagation Delay
PWM Minimum On-Time
t
PD_TRI_R
t
TSHO
t
PD_OFF_GH
t
PD_ON_GH
t
PD_OFF_GL
t
PD_ON_GL
t
PD_DSBL#_F
t
PWM_ON_MIN
Fig. 5
No load, see fig. 4
-
-
-
-
-
-
-
30
30
130
15
10
12
10
15
-
-
-
-
-
-
-
-
-
ns
V
TH_PWM_R
V
TH_PWM_F
V
TRI
V
TRI_TH_R
V
TRI_TH_F
V
HYS_TRI_R
V
HYS_TRI_F
I
PWM
V
PWM
= 3.3 V
V
PWM
= 0 V
V
PWM
= FLOAT
2.2
0.72
-
0.9
1.95
-
-
-
-
2.45
0.9
1.8
1.15
2.2
250
300
-
-
2.7
1.1
-
1.38
2.45
-
mV
-
225
-225
μA
V
V
TH_PWM_R
V
TH_PWM_F
V
TRI
V
TRI_TH_R
V
TRI_TH_F
V
HYS_TRI_R
V
HYS_TRI_F
I
PWM
V
PWM
= 5 V
V
PWM
= 0 V
V
PWM
= FLOAT
3.4
0.72
-
0.9
3
-
-
-
-
3.8
0.9
2.3
1.15
3.3
225
325
-
-
4.2
1.2
-
1.38
3.6
-
mV
-
350
-350
μA
V
V
F
I
F
= 2 mA
0.4
V
-
-
-
-
-
-
-
12
300
380
15
50
25
60
-
-
-
25
-
-
-
mA
μA
μA
SYMBOL
TEST CONDITION
LIMITS
MIN.
TYP.
MAX.
UNIT
Vishay Siliconix
S14-2189, Rev. A 03-Nov-14
Document Number: 63589
4
For technical questions, contact:
powerictechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
SiC620R, SiC620AR
www.vishay.com
ELECTRICAL SPECIFICATIONS
(DSBL# = ZCD_EN# = 5 V, V
IN
= 12 V, V
DRV
and V
CIN
= 5 V, T
A
= 25 °C)
PARAMETER
DSBL# ZCD_EN# INPUT
DSBL# Logic Input Voltage
ZCD_EN# Logic Input Voltage
PROTECTION
Under Voltage Lockout
Under Voltage Lockout Hysteresis
THWn Flag Set
(2)
THWn Flag
Clear
(2)
THWn Flag Hysteresis
(2)
THWn Output Low
V
UVLO
V
UVLO_HYST
T
THWn_SET
T
THWn_CLEAR
T
THWn_HYST
V
OL_THWn
I
THWn
= 2 mA
V
CIN
rising, on threshold
V
CIN
falling, off threshold
-
2.7
-
-
-
-
-
3.7
3.1
575
160
135
25
0.02
4.1
-
-
-
-
-
-
V
°C
V
mV
V
IH_DSBL#
V
IL_DSBL#
V
IH_ZCD_EN#
V
IL_ZCD_EN#
Input logic high
Input logic low
Input logic high
Input logic low
2
-
2
-
-
-
-
-
-
0.8
-
0.8
V
SYMBOL
TEST CONDITION
LIMITS
MIN.
TYP.
MAX.
UNIT
Vishay Siliconix
Notes
(1)
Typical limits are established by characterization and are not production tested.
(2)
Guaranteed by design.
DETAILED OPERATIONAL DESCRIPTION
PWM Input with Tri-state Function
The PWM input receives the PWM control signal from the VR
controller IC. The PWM input is designed to be compatible
with standard controllers using two state logic (H and L) and
advanced controllers that incorporate tri-state logic (H, L
and tri-state) on the PWM output. For two state logic, the
PWM input operates as follows. When PWM is driven above
V
PWM_TH_R
the low-side is turned on and the high-side is
turned on. When PWM input is driven below V
PWM_TH_F
the
high-side is turned OFF and the low-side is turned ON. For
tri-state logic, the PWM input operates as previously stated
for driving the MOSFETs. However, there is an third state
that is entered as the PWM output of tri-state compatible
controller enters its high impedance state during shut-down.
The high impedance state of the controller’s PWM output
allows the SiC620R and SiC620AR to pull the PWM input
into the tri-state region (see PWM Timing Diagram). If the
PWM input stays in this region for the tri-state hold-off
period, t
TSHO
, both high-side and low-side MOSFETs are
turned OFF. This function allows the VR phase to be
disabled without negative output voltage swing caused by
inductor ringing and saves a Schottky diode clamp. The
PWM and tri-state regions are separated by hysteresis to
prevent false triggering. The SiC620AR incorporates PWM
voltage thresholds that are compatible with 3.3 V logic and
the SiC620R thresholds are compatible with 5 V logic.
Disable (DSBL#)
In the low state, the DSBL# pin shuts down the driver IC and
disables both high-side and low-side MOSFETs. In this
state, standby current is minimized. If DSBL# is left
unconnected, an internal pull-down resistor will pull the pin
to C
GND
and shut down the IC.
S14-2189, Rev. A 03-Nov-14
Diode Emulation Mode (ZCD_EN#)
When ZCD_EN# pin is logic Low and PWM signal switches
Low, GL is forced on (after normal BBM time). During this
time, it is under control of the ZCD (zero crossing detect)
comparator. If, after the internal blanking delay, the inductor
current becomes zero, the low-side is turned off. This
improves light load efficiency by avoiding discharge of
output capacitors. If PWM enters tri-state, then device will
go into normal tri-state mode after tri-state delay. The GL
output will be turned off regardless of Inductor current, this
is an alternative method of improving light load efficiency by
reducing switching losses.
Thermal Shutdown Warning (THWn)
The THWn pin is an open drain signal that flags the presence
of excessive junction temperature. Connect with a
maximum of 20 kΩ, to V
CIN
. An internal temperature sensor
detects the junction temperature. The temperature
threshold is 160 °C. When this junction temperature is
exceeded the THWn flag is set. When the junction
temperature drops below 135 °C the device will clear the
THWn signal. The SiC620R and SiC620AR do not stop
operation when the flag is set. The decision to shutdown
must be made by an external thermal control function.
Voltage Input (V
IN
)
This is the power input to the drain of the high-side power
MOSFET. This pin is connected to the high power
intermediate BUS rail.
Document Number: 63589
5
For technical questions, contact:
powerictechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
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