CY28401
100 MHz Differential Buffer for PCI Express and SATA
Features
• CK409 or CK410 companion buffer
• Eight differential 0.7V clock pairs
• Individual OE controls
• Low CTC jitter (< 50 ps)
• Programmable bandwidth
• SRC_STOP# power management control
• SMBus Block/Byte/Word Read and Write support
• 3.3V operation
• PLL Bypass-configurable
• Divide by 2 programmable
• 48-pin SSOP package
Functional Description
The CY28401 is a differential buffer and serves as a
companion device to the CK409 or CK410 clock generator.
The device is capable of distributing the Serial Reference
Clock (SRC) in PCI Express and SATA implementations.
Block Diagram
Pin Configuration
SRC_DIV2#
VDD
VSS
SRCT_IN
SRCC_IN
OE_0
OE_3
DIFT0
DIFCO
VSS
VDD
DIFT1
DIFC1
OE_1
OE_2
DIFT2
DIFC2
VSS
VDD
DIFT3
DIFC3
PLL/BYPASS#
SCLK
SDATA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
VDD_A
VSS_A
IREF
LOCK
OE_7
OE_4
DIFT7
DIFC7
VSS
VDD
DIFT6
DIFC6
OE_6
OE_5
DIFT5
DIFC5
VSS
VDD
DIFT4
DIFC4
HIGH_BW#
SRC_STOP#
PWRDWN#
VSS
DIFT0
OE_[0:7]
SRC_STOP#
PWRDWN#
DIFC0
Output
Control
DIFT1
DIFC1
DIFT2
SCLK
SDATA
SRC_DIV2#
PLL/BYPASS#
SMBus
Controller
Output
Buffer
DIFC2
DIFT3
DIFC3
DIFT4
DIFC4
DIFT5
DIFC5
CY28401
SRCT_IN
SRCC_IN
DIV
HIGH_BW#
DIFT6
DIFC6
PLL
DIFT7
DIFC7
LOCK
48 SSOP
........................ Document #: 38-07592 Rev. *A Page 1 of 13
400 West Cesar Chavez, Austin, TX 78701
1+(512) 416-8500
1+(512) 416-9669
www.silabs.com
CY28401
Pin Description
Pin
4,5
Name
SRCT_IN, SRCC_IN
Type
I,DIF
Description
0.7V Differential SRC inputs from the clock synthesizer
8,9,12,13,16,17,20,21,29,30, DIFT/C(7:0)
33,34,37,38,41,42
6,7,14,15,35,36,43,44
28
45
26
1
27
23
24
46
22
48
47
3,10,18,25,32,40
2,11,19,31,39
OE_(7:0)
HIGH_BW#
LOCK
PWRDWN#
SRC_DIV/2#
SRC_STOP#
SCLK
SDATA
IREF
PLL/BYPASS#
VDD_A
VSS_A
VSS
VDD
O,DIF
0.7V Differential Clock Outputs
I,SE
I,SE
O,SE
I,SE
I,SE
I,SE
I,SE
I
I
3.3V
GND
I
I
3.3V LVTTL active LOW input for three-stating differential
outputs
3.3V LVTTL input for selecting PLL bandwidth
3.3V LVTTL output, transitions high when PL lock is
achieved (latched output)
3.3V LVTTL input for Power-down, active LOW
3.3V LVTTL input for selecting input frequency divided by
two, active LOW
3.3V LVTTL input for SRC_Stop#, active LOW
SMBus Slave Clock Input
A precision resistor is attached to this pin to set the differ-
ential output current
3.3V LVTTL input for selecting fan-out or PLL operation
3.3V Power Supply for PLL
Ground for PLL
Ground for outputs
3.3V power supply for outputs
I/O,OC
Open collector SMBus data
Serial Data Interface
To enhance the flexibility and function of the clock buffer, a
two-signal serial interface is provided. Through the Serial Data
Interface, various device functions, such as individual clock
output buffers, can be individually enabled or disabled. The
registers associated with the Serial Data Interface initialize to
their default setting upon power-up, and therefore use of this
interface is optional. Clock device register changes are
normally made upon system initialization, if any are required.
The interface cannot be used during system operation for
power management functions.
Data Protocol
The clock driver serial protocol accepts byte write, byte read,
block write, and block read operations from the controller. For
block write/read operation, the bytes must be accessed in
sequential order from lowest to highest byte (most significant
bit first) with the ability to stop after any complete byte has
been transferred. For byte write and byte read operations, the
system controller can access individually indexed bytes. The
offset of the indexed byte is encoded in the command code,
as described in
Table 1.
The block write and block read protocol is outlined in
Table 2
while
Table 3
outlines the corresponding byte write and byte
read protocol. The slave receiver address is 11011100 (DCh).
Table 1. Command Code Definition
Bit
7
(6:0)
0 = Block read or block write operation
1 = Byte read or byte write operation
Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be
'0000000'
Description
Table 2. Block Read and Block Write Protocol
Block Write Protocol
Bit
1
2:8
9
Start
Slave address – 7 bits
Write = 0
Description
Bit
1
2:8
9
Start
Slave address – 7 bits
Write = 0
Block Read Protocol
Description
........................ Document #: 38-07592 Rev. *A Page 2 of 13
CY28401
Table 2. Block Read and Block Write Protocol
(continued)
Block Write Protocol
Bit
10
11:18
19
20:27
28
29:36
37
38:45
46
....
....
....
....
Description
Acknowledge from slave
Command Code – 8 bits
'00000000' stands for block operation
Acknowledge from slave
Byte Count from master – 8 bits
Acknowledge from slave
Data byte 0 from master – 8 bits
Acknowledge from slave
Data byte 1 from master – 8 bits
Acknowledge from slave
Data bytes from master/Acknowledge
Data Byte N – 8 bits
Acknowledge from slave
Stop
Bit
10
11:18
19
20
21:27
28
29
30:37
38
39:46
47
48:55
56
....
....
....
....
Table 3. Byte Read and Byte Write Protocol
Byte Write Protocol
Bit
1
2:8
9
10
11:18
Start
Slave address – 7 bits
Write = 0
Acknowledge from slave
Command Code – 8 bits
'100xxxxx' stands for byte operation, bits[6:0] of the
command code represents the offset of the byte to be
accessed
Acknowledge from slave
Data byte from master – 8 bits
Acknowledge from slave
Stop
Description
Bit
1
2:8
9
10
11:18
Start
Slave address – 7 bits
Write = 0
Acknowledge from slave
Command Code – 8 bits
'100xxxxx' stands for byte operation, bits[6:0]
of the command code represents the offset of
the byte to be accessed
Acknowledge from slave
Repeat start
Slave address – 7 bits
Read = 1
Acknowledge from slave
Data byte from slave – 8 bits
Acknowledge from master
Stop
Byte Read Protocol
Description
Block Read Protocol
Description
Acknowledge from slave
Command Code – 8 bits
'00000000' stands for block operation
Acknowledge from slave
Repeat start
Slave address – 7 bits
Read = 1
Acknowledge from slave
Byte count from slave – 8 bits
Acknowledge from host
Data byte 0 from slave – 8 bits
Acknowledge from host
Data byte 1 from slave – 8 bits
Acknowledge from host
Data bytes from slave/Acknowledge
Data byte N from slave – 8 bits
Acknowledge from host
Stop
19
20:27
28
29
19
20
21:27
28
29
30:37
38
39
Byte 0: Control Register 0
Bit
7
6
@pup
0
0
Name
Description
PWRDWN# drive mode
0 = Driven when stopped, 1 = Three-state
SRC_STOP# drive mode
0 = Driven when stopped, 1 = Three-state
........................ Document #: 38-07592 Rev. *A Page 3 of 13
CY28401
Byte 0: Control Register 0
(continued)
Bit
5
4
3
2
1
0
@pup
0
0
0
1
1
1
Name
Reserved
Reserved
Reserved
HIGH_BW#
0 = High Bandwidth, 1 = Low bandwidth
PLL/Bypass#
0 = Fanout buffer, 1 = PLL mode
SRC_DIV/2
0 = Divided by 2 mode, 1 = Normal (output = input)
Description
Byte 1: Control Register 1
Bit
7
@pup
1
Name
DIF_7 Output Enable
0 = Disabled (three-state)
1 = Enabled
DIF_6 Output Enable
0 = Disabled (three-state)
1 = Enabled
DIF_5 Output Enable
0 = Disabled (three-state)
1 = Enabled
DIF_4 Output Enable
0 = Disabled (three-state)
1 = Enabled
DIF_3 Output Enable
0 = Disabled (three-state)
1 = Enabled
DIF_2 Output Enable
0 = Disabled (three-state)
1 = Enabled
DIF_1 Output Enable
0 = Disabled (three-state)
1 = Enabled
DIF_0 Output Enable
0 = Disabled (three-state)
1 = Enabled
Description
6
1
5
1
4
1
3
1
2
1
1
1
0
1
Byte 2: Control Register 2
Bit
7
@pup
0
Name
Description
Allow Control DIF_7 with assertion of SRC_STOP#
0 = Free-running
1 = Stopped with SRC_STOP#
Allow Control DIF_6 with assertion of SRC_STOP#
0 = Free-running
1 = Stopped with SRC_STOP#
Allow Control DIF_5 with assertion of SRC_STOP#
0 = Free-running
1 = Stopped with SRC_STOP#
Allow Control DIF_4 with assertion of SRC_STOP#
0 = Free-running
1 = Stopped with SRC_STOP#
6
0
5
0
4
0
........................ Document #: 38-07592 Rev. *A Page 4 of 13
CY28401
Byte 2: Control Register 2
(continued)
Bit
3
@pup
0
Name
Description
Allow Control DIF_3 with assertion of SRC_STOP#
0 = Free-running
1 = Stopped with SRC_STOP#
Allow Control DIF_2 with assertion of SRC_STOP#
0 = Free-running
1 = Stopped with SRC_STOP#
Allow Control DIF_1 with assertion of SRC_STOP#
0 = Free-running
1 = Stopped with SRC_STOP#
Allow Control DIF_0 with assertion of SRC_STOP#
0 = Free-running
1 = Stopped with SRC_STOP#
2
0
1
0
0
0
Byte 3: Control Register 3
Bit
7
6
5
4
3
2
1
0
@pup
0
0
0
0
0
0
0
0
Name
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Description
Byte 4: Vendor ID Register
Bit
7
6
5
4
3
2
1
0
@Pup
0
0
0
0
1
0
0
0
Name
Revision Code Bit 3
Revision Code Bit 2
Revision Code Bit 1
Revision Code Bit 0
Vendor ID Bit 3
Vendor ID Bit 2
Vendor ID Bit 1
Vendor ID Bit 0
Description
Byte 5: Control Register 5
Bit
7
6
5
4
3
2
1
0
@Pup
0
0
0
0
0
0
0
0
Name
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Description
........................ Document #: 38-07592 Rev. *A Page 5 of 13
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