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70V25L35J

产品描述SRAM 8Kx16, 3.3V DUAL- PORT RAM
产品类别存储   
文件大小747KB,共27页
制造商IDT(艾迪悌)
官网地址http://www.idt.com/
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70V25L35J概述

SRAM 8Kx16, 3.3V DUAL- PORT RAM

70V25L35J规格参数

参数名称属性值
产品种类
Product Category
SRAM
制造商
Manufacturer
IDT(艾迪悌)
RoHSNo
封装 / 箱体
Package / Case
PLCC-84
系列
Packaging
Tube
高度
Height
3.63 mm
长度
Length
29.21 mm
Moisture SensitiveYes
工厂包装数量
Factory Pack Quantity
15
宽度
Width
29.21 mm

文档预览

下载PDF文档
HIGH-SPEED 3.3V
8/4K x 18 DUAL-PORT
8/4K x 16 DUAL-PORT
STATIC RAM
IDT70V35/34S/L
IDT70V25/24S/L
Features
Functional Block Diagram
R/W
L
UB
L
True Dual-Ported memory cells which allow simultaneous
reads of the same memory location
High-speed access
IDT70V35/34
– Commercial: 15/20/25ns (max.)
– Industrial: 20ns
IDT70V25
– Commercial: 15/20/25/35/55ns (max.)
– Industrial: 20/25ns
IDT70V24
– Commercial: 15/20/25/35/55ns (max.)
– Industrial: 20ns
Low-power operation
– IDT70V35/34S
– IDT70V35/34L
Active: 430mW (typ.)
Active: 415mW (typ.)
Standby: 3.3mW (typ.)
Standby: 660
µ
W (typ.)
– IDT70V25/24S
– IDT70V25/24L
Active: 400mW (typ.)
Active: 380mW (typ.)
Standby: 3.3mW (typ.)
Standby: 660
µ
W (typ.)
Separate upper-byte and lower-byte control for multiplexed
bus compatibility
IDT70V35/34 (IDT70V25/24) easily expands data bus width
to 36 bits (32 bits) or more using the Master/Slave select
when cascading more than one device
M/S = V
IH
for
BUSY
output flag on Master
M/S = V
IL
for
BUSY
input on Slave
BUSY
and Interrupt Flag
On-chip port arbitration logic
Full on-chip hardware support of semaphore signaling
between ports
Fully asynchronous operation from either port
LVTTL-compatible, single 3.3V (±0.3V) power supply
Available in a 100-pin TQFP (IDT70V35/24) & (IDT70V25/24),
86-pin PGA (IDT70V25/24) and 84-pin PLCC (IDT70V25/24)
Industrial temperature range (-40°C to +85°C) is available
for selected speeds
Green parts available, see ordering information
R/W
R
UB
R
LB
L
CE
L
OE
L
LB
R
CE
R
OE
R
,
I/O
9L
-I/O
17L
(5)
I/O
Control
I/O
0L
-I/O
8L
(4)
BUSY
L
A
12L
(1)
A
0L
(2,3)
I/O
9R
-I/O
17R
(5)
I/O
Control
I/O
0R
-I/O
8R
(4)
BUSY
R
(2,3)
A
12R
(1)
A
0R
Address
Decoder
13
MEMORY
ARRAY
13
Address
Decoder
CE
L
OE
L
R/W
L
SEM
L
INT
L
(3)
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
CE
R
OE
R
R/W
R
SEM
R
INT
R
(3)
5624 drw 01
NOTES:
1. A
12
is a NC for IDT70V34 and for IDT70V24.
2. (MASTER):
BUSY
is output; (SLAVE):
BUSY
is input.
3.
BUSY
outputs and
INT
outputs are non-tri-stated push-pull.
4. I/O
0
x - I/O
7
x for IDT70V25/24.
5. I/O
8
x - I/O
15
x for IDT70V25/24.
©2015 Integrated Device Technology, Inc.
M/S
AUGUST 2015
1
DSC-5624/8

 
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