CY7C027V/027AV/028V/028AV
CY7C037AV/038V
3.3 V 32 K / 64 K × 16 / 18 Dual-Port
Static RAM
3.3 V 32 K / 64 K × 16 / 18 Dual-Port Static RAM
Features
True dual-ported memory cells which allow simultaneous
access of the same memory location
[1]
■
32 K × 16 organization (CY7C027V/027AV )
[1]
■
64 K × 16 organization (CY7C028V/028AV )
■
32 K × 18 organization (CY7C037AV)
■
64 K × 18 organization (CY7C038V)
■
0.35 micron Complementary metal oxide semiconductor
(CMOS) for optimum speed and power
■
High speed access: 15, 20, and 25 ns
■
Low operating power
■
Active: I
CC
= 115 mA (typical)
■
Standby: I
SB3
= 10
A
(typical)
■
Fully asynchronous operation
■
Automatic power-down
■
Expandable data bus to 32/36 bits or more using Master/Slave
chip select when using more than one device
■
On-chip arbitration logic
■
Semaphores included to permit software handshaking
between ports
■
INT flag for port-to-port communication
■
Separate upper-byte and lower-byte control
■
Dual chip enables
■
Pin select for Master or Slave
■
Commercial and Industrial temperature ranges
■
100-pin Pb-free Thin quad plastic flatpack (TQFP) and 100-pin
TQFP
For a complete list of related documentation,
click here.
■
Logic Block Diagram
R/W
L
UB
L
R/W
R
UB
R
CE
0L
CE
1L
LB
L
OE
L
CE
L
CE
R
CE
0R
CE
1R
LB
R
OE
R
I/O
8/9L
–I/O
15/17L
I/O
0L
–I/O
7/8L
[3]
[2]
8/9
8/9
8/9
I/O
Control
I/O
Control
8/9
I/O
8/9L
–I/O
15/17R
I/O
0L
–I/O
7/8R
[3]
[2]
A
0L
–A
14/15L
[4]
15/16
Address
Decode
15/16
True Dual-Ported
RAM Array
Address
Decode
15/16
15/16
A
0R
–A
14/15R
[4]
A
0L
–A
14/15L
CE
L
OE
L
R/W
L
SEM
L
BUSY
L
INT
L
UB
L
LB
L
[5]
[4]
Interrupt
Semaphore
Arbitration
A
0R
–A
14/15R
CE
R
OE
R
R/W
R
SEM
R
[5]
[4]
M/S
BUSY
R
INT
R
UB
R
LB
R
Notes
1. CY7C027V, and CY7C027AV are functionally identical. CY7C028V and CY7C028AV are functionally identical.
2. I/O
8
–I/O
15
for x16 devices; I/O
9
–I/O
17
for x18 devices.
3. I/O
0
–I/O
7
for x16 devices; I/O
0
–I/O
8
for x18 devices.
4. A
0
–A
14
for 32K; A
0
–A
15
for 64K devices.
5. BUSY is an output in master mode and an input in slave mode.
Cypress Semiconductor Corporation
Document Number: 38-06078 Rev. *I
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised November 20, 2014
CY7C027V/027AV/028V/028AV
CY7C037AV/038V
Contents
Pin Configurations ........................................................... 3
Selection Guide ................................................................ 5
Pin Definitions .................................................................. 5
Architecture ...................................................................... 5
Functional Description ..................................................... 5
Write Operation ........................................................... 5
Read Operation ........................................................... 6
Interrupts ..................................................................... 6
Busy ............................................................................ 6
Master/Slave ............................................................... 6
Semaphore Operation ................................................. 6
Maximum Ratings ............................................................. 7
Operating Range ............................................................... 7
Electrical Characteristics ................................................. 7
Capacitance ...................................................................... 7
AC Test Loads and Waveforms ....................................... 8
Data Retention Mode ........................................................ 8
Timing ................................................................................ 8
Switching Characteristics ................................................ 9
Switching Waveforms .................................................... 11
Non-Contending Read/Write .......................................... 17
Interrupt Operation Example ......................................... 17
Semaphore Operation Example .................................... 18
Ordering Information ...................................................... 19
32 K × 16 3.3 V Asynchronous Dual-Port SRAM ...... 19
64 K × 16 3.3 V Asynchronous Dual-Port SRAM ...... 19
32 K × 18 3.3 V Asynchronous Dual-Port SRAM ...... 19
64 K × 18 3.3 V Asynchronous Dual-Port SRAM ...... 19
Ordering Code Definitions ......................................... 20
Package Diagram ............................................................ 21
Acronyms ........................................................................ 22
Document Conventions ................................................. 22
Units of Measure ....................................................... 22
Document History Page ................................................. 23
Sales, Solutions, and Legal Information ...................... 24
Worldwide Sales and Design Support ....................... 24
Products .................................................................... 24
PSoC® Solutions ...................................................... 24
Cypress Developer Community ................................. 24
Technical Support ..................................................... 24
Document Number: 38-06078 Rev. *I
Page 2 of 24
CY7C027V/027AV/028V/028AV
CY7C037AV/038V
Pin Configurations
Figure 1. 100-pin TQFP pinout (Top View)
BUSYR
BUSYL
INTR
GND
INTL
A0R
A1R
A2R
A3R
A4R
A5R
A6R
A7R
A8R
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
M/S
A8L
A7L
A6L
A5L
A4L
A3L
A2L
A1L
A0L
NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
A9L
A10L
A11L
A12L
A13L
A14L
[6] A15L
NC
NC
LBL
UBL
CE0L
CE1L
SEML
VCC
R/WL
OEL
GND
GND
I/O15L
I/O14L
I/O13L
I/O12L
I/O11L
I/O10L
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
A9R
A10R
A11R
A12R
A13R
A14R
A15R [6]
NC
NC
LBR
UBR
CE0R
CE1R
SEMR
GND
R/WR
OER
GND
GND
I/O15R
I/O14R
I/O13R
I/O12R
I/O11R
I/O10R
CY7C028V/028AV (64 K × 16)
CY7C027V/027AV (32 K × 16)
I/O9L
I/O8L
I/O7L
I/O6L
I/O5L
I/O4L
I/O3L
I/O2L
I/O1L
I/O0L
I/O0R
I/O2R
I/O3R
I/O4R
I/O5R
I/O6R
I/O7R
I/O8R
I/O9R
GND
GND
I/01R
VCC
VCC
Note
6. This pin is NC for CY7C027V/027AV.
Document Number: 38-06078 Rev. *I
NC
Page 3 of 24
CY7C027V/027AV/028V/028AV
CY7C037AV/038V
Pin Configurations(continued)
Figure 2. 100-pin TQFP pinout (Top View)
BUSYR
BUSYL
INTR
GND
GND
INTL
VCC
A0R
A1R
A2R
A3R
A4R
A5R
A6R
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
A9L
A10L
A11L
A12L
A13L
A14L
[7]
A15L
LBL
UBL
CE0L
CE1L
SEML
R/WL
OEL
VCC
GND
I/O17L
I/O16L
GND
I/O15L
I/O14L
I/O13L
I/O12L
I/O11L
I/O10L
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A8R
A9R
A10R
A11R
A12R
A13R
A14R
A15R [7]
LBR
UBR
CE0R
CE1R
SEMR
R/WR
GND
OER
GND
I/O17R
GND
I/O16R
I/O15R
I/O14R
I/O13R
I/O12R
I/O11R
CY7C038V (64K x 18)
CY7C037AV (32K x 18)
I/O9L
I/O8L
I/O7L
I/O6L
I/O5L
I/O4L
I/O3L
I/O2L
I/O1L
I/O0L
I/O2R
I/O4R
I/O6R
I/O7R
I/O8R
I/O9R
Note
7. This pin is NC for CY7C037AV.
Document Number: 38-06078 Rev. *I
I/O10R
I/O0R
I/01R
I/O3R
I/O5R
GND
GND
VCC
VCC
A7R
M/S
A8L
A7L
A6L
A5L
A4L
A3L
A2L
A1L
A0L
Page 4 of 24
CY7C027V/027AV/028V/028AV
CY7C037AV/038V
Selection Guide
Parameter
Maximum access time
Typical operating current
Typical standby current for I
SB1
(Both ports TTL level)
Typical standby current for I
SB3
(Both ports CMOS level)
-15
15
125
35
10
-20
20
120
35
10
-25
25
115
30
10
Unit
ns
mA
mA
A
Pin Definitions
Left Port
CE
0L
, CE
1L
R/W
L
OE
L
A
0L
–A
15L
I/O
0L
–I/O
17L
SEM
L
UB
L
LB
L
INT
L
BUSY
L
M/S
V
CC
GND
NC
Right Port
CE
0R
, CE
1R
R/W
R
OE
R
A
0R
–A
15R
SEM
R
UB
R
LB
R
INT
R
BUSY
R
Read/Write Enable
Output Enable
Address (A
0
–A
14
for 32K; A
0
–A
15
for 64K devices)
Semaphore Enable
Upper byte select (I/O
8
–I/O
15
for × 16 devices; I/O
9
–I/O
17
for × 18 devices)
Lower byte select (I/O
0
–I/O
7
for × 16 devices; I/O
0
–I/O
8
for × 18 devices)
Interrupt flag
Busy flag
Master or Slave select
Power
Ground
No connect
function as a 32/36-bit or wider master/slave dual-port static
RAM. An M/S pin is provided for implementing 32/36-bit or wider
memory applications without the need for separate master and
slave devices or additional discrete logic. Application areas
include interprocessor/multiprocessor designs, communications
status buffering, and dual-port video/graphics memory.
Each port has independent control pins: Chip Enable (CE), Read
or Write Enable (R/W), and Output Enable (OE). Two flags are
provided on each port (BUSY and INT). BUSY signals that the port is
trying to access the same location currently being accessed by the other
port. The interrupt flag (INT) permits communication between ports or
systems by means of a mail box. The semaphores are used to pass a
flag, or token, from one port to the other to indicate that a shared
resource is in use. The semaphore logic is comprised of eight shared
latches. Only one side can control the latch (semaphore) at any time.
Control of a semaphore indicates that a shared resource is in use. An
automatic power down feature is controlled independently on each port
by a chip select (CE) pin.
The CY7C027V/027AV/028V/028AV and CY7037AV/038V are
available in 100-pin Thin Quad Plastic Flatpacks (TQFP).
Description
Chip Enable (CE is LOW when CE
0
V
IL
and CE
1
V
IH
)
I/O
0R
–I/O
17R
Data bus input/output (I/O
0
–I/O
15
for × 16 devices; I/O
0
–I/O
17
for × 18)
Architecture
The CY7C027V/027AV/028V/028AV and CY7037AV/038V
consist of an array of 32K and 64K words of 16 and 18 bits each
of dual-port RAM cells, I/O and address lines, and control signals
(CE, OE, R/W). These control pins permit independent access for reads
or writes to any location in memory. To handle simultaneous
writes/reads to the same location, a BUSY pin is provided on each port.
Two interrupt (INT) pins can be utilized for port-to-port communication.
Two semaphore (SEM) control pins are used for allocating shared
resources. With the M/S pin, the devices can function as a master
(BUSY pins are outputs) or as a slave (BUSY pins are inputs). The
devices also have an automatic power down feature controlled by CE.
Each port is provided with its own output enable control (OE), which
allows data to be read from the device.
Functional Description
The CY7C027V/027AV/028V/028AV and CY7037AV/038V are
low power CMOS 32K, 64K x 16/18 dual-port static RAMs.
Various arbitration schemes are included on the devices to
handle situations when multiple processors access the same
piece of data. Two ports are provided, permitting independent,
asynchronous access for reads and writes to any location in
memory. The devices can be utilized as stand-alone 16/18-bit
dual-port static RAMs or multiple devices can be combined to
Document Number: 38-06078 Rev. *I
Write Operation
Data must be set up for a duration of t
SD
before the rising edge of
R/W to guarantee a valid write. A write operation is controlled by either
the R/W pin (see
Figure 7)
or the CE pin (see
Figure 8).
Required inputs
Page 5 of 24
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