NBSG16M
2.5 V/3.3 V Multilevel Input
to CML Clock/Data
Receiver/Driver/Translator
Buffer
Description
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MARKING
DIAGRAM*
16
1
The NBSG16M is a differential current mode logic (CML)
receiver/driver/translator buffer. The device is functionally equivalent
to the EP16, LVEP16, or SG16 devices with CML output structure and
lower EMI capabilities.
Inputs incorporate internal 50
W
termination resistors and accept
LVNECL (Negative ECL), LVPECL (Positive ECL), LVTTL,
LVCMOS, CML, or LVDS. The CML output structure contains
internal 50
W
source termination resistor to V
CC
. The device
generates 400 mV output amplitude with 50
W
receiver resistor to
V
CC
.
The V
BB
pin is internally generated voltage supply available to this
device only. For all single−ended input conditions, the unused
complementary differential input is connected to V
BB
as a switching
reference voltage. V
BB
may also rebias AC coupled inputs. When
used, decouple V
BB
via a 0.01
mF
capacitor and limit current sourcing
or sinking to 0.5 mA. When not used, V
BB
output should be left open.
Features
1
QFN−16
MN SUFFIX
CASE 485G
SG
16M
ALYW
G
G
A
L
Y
W
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
•
•
•
•
•
•
•
•
•
•
•
Maximum Input Clock Frequency > 10 GHz Typical
Maximum Input Data Rate > 10 Gb/s Typical
120 ps Typical Propagation Delay
35 ps Typical Rise and Fall Times
Positive CML Output with Operating Range:
V
CC
= 2.375 V to 3.465 V with V
EE
= 0 V
Negative CML Output with RSNECL or NECL Inputs with
Operating Range: V
CC
= 0 V with V
EE
=
−2.375
V to
−3.465
V
CML Output Level; 400 mV Peak−to−Peak Output with
50
W
Receiver Resistor to V
CC
50
W
Internal Input and Output Termination Resistors
Compatible with Existing 2.5 V/3.3 V LVEP, EP, LVEL
and SG Devices
V
BB
Reference Voltage Output
Pb−Free Packages are Available
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 10 of this data sheet.
©
Semiconductor Components Industries, LLC, 2009
March, 2009
−
Rev. 7
1
Publication Order Number:
NBSG16M/D
NBSG16M
V
CC
V
BB
16
VTD
D
D
VTD
1
2
NBSG16M
3
4
5
V
CC
6
NC
7
V
EE
8
V
EE
10
9
Q
V
CC
15
V
EE
14
V
EE
13
12
11
Exposed Pad (EP)
V
CC
Q
Figure 1. QFN−16 Pinout
(Top View)
Table 1. PIN DESCRIPTION
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
−
Name
V
TD
D
D
I/O
−
Description
LVDS, CML, ECL, LVTTL,
LVCMOS Input
LVDS, CML, ECL, LVTTL,
LVCMOS Input
−
−
−
−
−
−
CML Output
CML Output
−
−
−
−
−
−
V
TD
V
CC
NC
V
EE
V
EE
V
CC
Q
Q
V
CC
V
EE
V
EE
V
BB
V
CC
EP
1. The NC pins are electrically connected to the die and MUST be left open.
2. CML outputs require 50
W
receiver termination resistor to V
CC
for proper operation.
3. In the differential configuration when the input termination pin (V
TD
, V
TD
) are connected to a common termination voltage, and if no signal
is applied then the device will be susceptible to self−oscillation.
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Inverted Differential Input (Note 3)
Noninverted Differential Input. (Note 3)
Internal 50
W
Termination Pin. See Table 2. (Note 3)
Positive Supply Voltage. All V
CC
pins must be externally connected to Power Supply to guar-
antee proper operation.
No Connect (Note 1)
Negative Supply Voltage. All V
EE
pins must be externally connected to Power Supply to guar-
antee proper operation.
Negative Supply Voltage. All V
EE
pins must be externally connected to Power Supply to guar-
antee proper operation.
Positive Supply Voltage. All V
CC
pins must be externally connected to Power Supply to guar-
antee proper operation.
Noninverted CML Differential Output with Internal 50
W
Source Termination Resistor. (Note 2)
Inverted CML Differential Output with Internal 50
W
Source Termination Resistor. (Note 2)
Positive Supply Voltage. All V
CC
pins must be externally connected to Power Supply to guar-
antee proper operation.
Negative Supply Voltage. All V
EE
pins must be externally connected to Power Supply to guar-
antee proper operation.
Negative Supply Voltage. All V
EE
pins must be externally connected to Power Supply to guar-
antee proper operation.
Internally Generated ECL Reference Output Voltage
Positive Supply Voltage. All V
CC
pins must be externally connected to Power Supply to guar-
antee proper operation.
The Exposed Pad (EP) and the QFN−16 package bottom is thermally connected to the die
for improved heat transfer out of package. The exposed pad must be attached to a heat−
sinking conduit. The pad is not electrically connected to the die but may be electrically and
thermally connected to V
EE
on the PC board.
Internal 50
W
Termination Pin. See Table 2. (Note 3)
ÁÁÁÁÁ
Á
ÁÁÁÁÁ
Á
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2
NBSG16M
V
CC
V
CC
VTD
50
W
D
D
50
W
VTD
V
BB
16 mA
V
EE
V
EE
50
W
50
W
Q
Q
50
W
50
W
Q
Q
Figure 2. Logic Diagram
Figure 3. CML Output Structure
Table 2. Interfacing Options
INTERFACING OPTIONS
CML
LVDS
AC−COUPLED
RSECL, PECL, NECL
LVTTL, LVCMOS
CONNECTIONS
Connect VTD and VTD to V
CC
Connect VTD and VTD together
Bias VTD and VTD Inputs within (V
IHCMR
)
Common Mode Range
Standard ECL Termination Techniques
An external voltage should be applied to the
unused complementary differential input.
Nominal voltage 1.5 V for LVTTL and V
CC
/2 for
LVCMOS inputs.
Table 3. ATTRIBUTES
Characteristics
ESD Protection
Human Body Model
Machine Model
Charged Device Model
Pb Pkg
Level 1
Value
> 1 kV
> 100 V
> 4 kV
Pb−Free Pkg
Level 1
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 4)
QFN−16
Flammability Rating
Transistor Count
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
Oxygen Index: 28 to 34
UL 94 V−0 @ 0.125 in
145
4. For additional Moisture Sensitivity information, refer to Application Note AND8003/D.
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3
NBSG16M
Table 4. MAXIMUM RATINGS
Symbol
V
CC
V
EE
V
I
V
INPP
I
IN
I
out
I
BB
T
A
T
stg
q
JA
q
JC
T
sol
Parameter
Positive Power Supply
Negative Power Supply
Positive Input
Negative Input
Differential Input Voltage |D
−
D|
Input Current Through R
T
(50
W
Resistor)
Output Current
V
BB
Sink/Source
Operating Temperature Range
Storage Temperature Range
Thermal Resistance (Junction−to−Ambient)
(Note 5)
Thermal Resistance (Junction−to−Case)
Wave Solder
Pb
Pb−Free
0 lfpm
500 lfpm
1S2P (Note 5)
<2 to 3 sec @ 248°C
<2 to 3 sec @ 260°C
QFN−16
QFN−16
QFN−16
Condition 1
V
EE
= 0 V
V
CC
= 0 V
V
EE
= 0 V
V
CC
= 0 V
V
CC
−
V
EE
w
2.8 V
V
CC
−
V
EE
< 2.8 V
Static
Surge
Continuous
Surge
V
I
v
V
CC
V
I
w
V
EE
Condition 2
Rating
3.6
−3.6
3.6
−3.6
2.8
|V
CC
−
V
EE
|
45
80
25
50
1.0
−40
to +85
−65
to +150
42
35
4.0
265
265
Unit
V
V
V
V
V
mA
mA
mA
mA
mA
°C
°C
°C/W
°C/W
°C/W
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may
affect device reliability.
5. JEDEC standard multilayer board
−
1S2P (1 signal, 2 power)
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NBSG16M
Table 5. DC CHARACTERISTICS, POSITIVE CML OUTPUT
V
CC
= 2.5 V; V
EE
= 0 V (Note 6)
−40°C
Symbol
I
CC
V
OH
V
OL
V
IH
V
IL
V
BB
V
IHCMR
Characteristic
Positive Power Supply Current
Output HIGH Voltage (Note 7)
Output LOW Voltage (Note 6)
Input HIGH Voltage
(Single−Ended) (Note 8)
Input LOW Voltage
(Single−Ended) (Note 8)
ECL Reference Voltage Output
Input HIGH Voltage Common Mode
Range (Note 8)
(Differential Configuration)
Internal Input Termination Resistor
Internal Output Termination
Resistor
Input HIGH Current (@ V
IH
)
Input LOW Current (@ V
IL
)
V
EE
+
1.275
V
EE
1075
1.2
Min
37
V
CC
−
40
Typ
43
V
CC
−
10
V
CC
−
400
V
CC
−
1.0*
V
CC
−
1.4*
1170
Max
51
V
CC
V
CC
−
330
V
CC
V
IH
−
0.150
1265
2.5
V
EE
+
1.275
V
EE
1075
1.2
Min
37
V
CC
−
40
25°C
Typ
43
V
CC
−
10
V
CC
−
400
V
CC
−
1.0*
V
CC
−
1.4*
1170
Max
51
V
CC
V
CC
−
330
V
CC
V
IH
−
0.150
1265
2.5
V
EE
+
1..275
V
EE
1075
1.2
Min
37
V
CC
−
40
85°C
Typ
43
V
CC
−
10
V
CC
−
400
V
CC
−
1.0*
V
CC
−
1.4*
1170
Max
51
V
CC
V
CC
−
330
V
CC
V
IH
−
0.150
1265
2.5
Unit
mA
mV
mV
V
V
mV
V
R
TIN
R
TOUT
I
IH
I
IL
45
45
50
50
60
25
55
55
100
50
45
45
50
50
60
25
55
55
100
50
45
45
50
50
60
25
55
55
100
50
W
W
mA
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification
limit values are applied individually under normal operating conditions and not valid simultaneously.
6. Input and output parameters vary 1:1 with V
CC
. V
EE
can vary +0.125 V to
−0.965
V.
7. All loading with 50
W
to V
CC
.
8. V
IHCMR
min varies 1:1 with V
EE
, V
IHCMR
max varies 1:1 with V
CC
. The V
IHCMR
range is referenced to the most positive side of the differen-
tial input signal.
*Typicals used for testing purposes.
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