FemtoClock™ Crystal-to-LVCMOS/LVTTL
Frequency Synthesizer
840004-01
DATA SHEET
General Description
The 840004-01 is a 4 output LVCMOS/LVTTL Synthesizer
optimized to generate Ethernet reference clock frequencies. Using
a 25MHz, 18pF parallel resonant crystal, the following frequencies
can be generated based on the 2 frequency select pins
(F_SEL1:0): 156.25MHz, 125MHz, and 62.5MHz. The 840004-01
uses IDT’s 3
rd
generation low phase noise VCO technology and
can achieve 1ps or lower typical random rms phase jitter, easily
meeting Ethernet jitter requirements. The 840004-01 is packaged
in a small 20-pin TSSOP package.
Features
•
•
•
•
•
Four single-ended LVCMOS/LVTTL outputs
17
typical output impedance
Selectable crystal oscillator interface or single-ended input
Output frequency range: 56MHz - 175MHz
VCO range: 560MHz - 700MHz
RMS phase jitter at 156.25MHz (1.875MHz – 20MHz):
0.52ps (typical)
Phase Noise:
Offset
Noise Power
100Hz
-94.9 dBc/Hz
1kHz
-119.6 dBc/Hz
10kHz
-128.9 dBc/Hz
100kHz
-129.2 dBc/Hz
•
•
•
Frequency Select Function Table for Ethernet Frequencies
Inputs
F_SEL1
0
0
1
1
F_SEL0
0
1
0
1
M Div. Value
25
25
25
25
N Div. Value
4
5
10
5
Full 3.3V or mixed 3.3V core/2.5V output supply modes
0°C to 70°C ambient operating temperature
Available in lead-free (RoHS 6) package
M/N Ratio Value
6.25
5
2.5
5
Output Frequency (MHz), (25MHz Reference)
156.25
125
62.5
125 (default)
Block Diagram
OE
F_SEL1:0
nPLL_SEL
nXTAL_SEL
Pullup
Pullup:Pullup
Pulldown
Pulldown
25MHz
Pin Assignment
2
F_SEL0
nc
nXTAL_SEL
REF_CLK
OE
MR
nPLL_SEL
V
DDA
nc
V
DD
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
F_SEL1
GND
Q0
Q1
V
DDO
Q2
Q3
GND
XTAL_IN
XTAL_OUT
XTAL_IN
OSC
XTAL_OUT
REF_CLK
Pulldown
0
F_SEL1:0
1
Phase
Detector
00
01
10
11
Q0
1
VCO
0
N
÷4
÷5
÷10
÷5
(default)
Q1
840004-01
20-Lead TSSOP
6.5mm x 4.4mm x 0.925mm
package body
G Package
Top View
Q2
M = ÷25 (fixed)
Q3
MR
Pulldown
840004-01 Rev B 4/2/15
1
©2015 Integrated Device Technology, Inc.
840004-01 DATA SHEET
Table 1. Pin Descriptions
Number
1, 20
2, 9
3
4
5
Name
F_SEL0,
F_SEL1
nc
nXTAL_SEL
REF_CLK
OE
Input
Unused
Input
Input
Input
Pulldown
Pulldown
Pullup
Type
Pullup
Description
Frequency select pins. LVCMOS/LVTTL interface levels.
No connect.
Selects between the crystal or REF_CLK inputs as the PLL reference
source. When HIGH, selects REF_CLK. When LOW, selects XTAL
inputs. LVCMOS/LVTTL interface levels.
Single-ended reference clock input. LVCMOS/LVTTL interface levels.
Output enable pin. When HIGH, the outputs are active. When LOW, the
outputs are in a high impedance state. LVCMOS/LVTTL interface levels.
Active HIGH master reset. When logic HIGH, the internal dividers are
reset causing the outputs to go low. When logic LOW, the internal
dividers and the outputs are enabled. LVCMOS/LVTTL interface levels.
PLL bypass. When LOW, the output is driven from the VCO output.
When HIGH, the PLL is bypassed and the output frequency = reference
clock frequency/N output divider. LVCMOS/LVTTL interface levels.
Analog supply pin.
Core supply pin.
Crystal oscillator interface. XTAL_IN is the input. XTAL_OUT is the
output.
Power supply ground.
Single-ended clock outputs. 17
typical output impedance.
LVCMOS/ LVTTL interface levels.
Output supply pin.
6
MR
Input
Pulldown
7
8
10
11,
12
13, 19
14, 15, 17, 18
16
nPLL_SEL
V
DDA
V
DD
XTAL_OUT,
XTAL_IN
GND
Q3, Q2, Q1, Q0
V
DDO
Input
Power
Power
Input
Power
Output
Power
Pulldown
NOTE:
Pullup and Pulldown
refer to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
C
PD
R
PULLUP
R
PULLDOWN
R
OUT
Parameter
Input Capacitance
Power Dissipation Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Output Impedance
V
DDO
= 3.3V±5%
V
DDO
= 2.5V±5%
Test Conditions
Minimum
Typical
4
8
51
51
17
21
Maximum
Units
pF
pF
k
k
Rev B 4/2/15
2
FEMTOCLOCK™ CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY
SYNTHESIZER
840004-01 DATA SHEET
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics or AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Supply Voltage, V
DD
Inputs, V
I
Outputs, V
O
Package Thermal Impedance,
JA
Storage Temperature, T
STG
Rating
4.6V
-0.5V to V
DD
+ 0.5V
-0.5V to V
DDO
+ 0.5V
73.2C/W (0 lfpm)
-65C to 150C
DC Electrical Characteristics
Table 3A. Power Supply DC Characteristics,
V
DD
= 3.3V ± 5%, V
DDO
= 3.3V ± 5% or 2.5V ± 5%, T
A
= 0°C to 70°C
Symbol
V
DD
V
DDA
V
DDO
I
DD
I
DDA
I
DDO
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
2.375
Power Supply Current
Analog Supply Current
Output Supply Current
2.5
2.625
100
12
10
V
mA
mA
mA
Test Conditions
Minimum
3.135
3.135
3.135
Typical
3.3
3.3
3.3
Maximum
3.465
3.465
3.465
Units
V
V
V
Table 3B. LVCMOS/LVTTL DC Characteristics,
V
DD
= 3.3V ± 5%, V
DDO
= 3.3V ± 5% or 2.5V ± 5%, T
A
= 0°C to 70°C
Symbol
V
IH
V
IL
Parameter
Input High Voltage
Input Low Voltage
nXTAL_SEL,
nPLL_SEL,
REF_CLK, MR
OE, F_SEL[0:1]
nXTAL_SEL,
nPLL_SEL,
REF_CLK, MR
OE, F_SEL[0:1]
V
OH
V
OL
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Test Conditions
V
DD
= 3.465V
V
DD
= 3.465V
V
DD
= V
IN
= 3.465V
V
DD
= V
IN
= 3.465V
V
DD
= 3.465V, V
IN
= 0V
V
DD
= 3.465V, V
IN
= 0V
V
DDO
= 3.3V ± 5%
V
DDO
= 2.5V ± 5%
V
DDO
= 3.3V ± 5% or 2.5V ± 5%
-5
-150
2.6
1.8
0.5
Minimum
2
-0.3
Typical
Maximum
V
DD
+ 0.3
0.8
150
5
Units
V
V
µA
µA
µA
µA
V
V
V
I
IH
Input
High Current
I
IL
Input
Low Current
NOTE 1: Outputs terminated with 50
to V
DDO
/2. See Parameter Measurement Information section.
Load Test Circuit diagrams.
FEMTOCLOCK™ CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY
SYNTHESIZER
3
Rev B 4/2/15
840004-01 DATA SHEET
Table 4. Crystal Characteristics
Parameter
Mode of Oscillation
Frequency
Equivalent Series Resistance (ESR)
Shunt Capacitance
Drive Level
Test Conditions
Minimum
Typical
Fundamental
25
50
7
1
MHz
Maximum
Units
pF
mW
AC Electrical Characteristics
Table 5A. AC Characteristics,
V
DD
= V
DDO
= 3.3V ± 5%, T
A
= 0°C to 70°C
Symbol
f
out
tsk(o)
Parameter
Output Frequency
Output Skew: NOTE 1, 2
156.25MHz, Integration Range:
1.875MHz – 20MHz
tjit(Ø)
RMS Phase Jitter (Random);
NOTE 3
125MHz, Integration Range:
1.875MHz – 20MHz
62.5MHz, Integration Range:
1.875MHz – 20MHz
t
R
/ t
F
odc
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
F_SEL[1:0] = 00, 01 or 11
F_SEL[1:0] = 10
200
43
49
0.52
0.65
0.55
700
57
51
Test Conditions
F_SEL[1:0] = 00
F_SEL[1:0] = 01 or 11
F_SEL[1:0] = 10
Minimum
140
112
56
Typical
156.25
125
62.5
Maximum
175
140
70
60
Units
MHz
MHz
MHz
MHz
ps
ps
ps
ps
%
%
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the
device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after
thermal equilibrium has been reached under these conditions.
NOTE 1: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at V
DDO
/2.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Please refer to the Phase Noise Plots.
Rev B 4/2/15
4
FEMTOCLOCK™ CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY
SYNTHESIZER
840004-01 DATA SHEET
Table 5B. AC Characteristics,
V
DD
= 3.3V ± 5%, V
DDO
= 2.5V ± 5%, T
A
= 0°C to 70°C
Symbol
f
out
tsk(o)
Parameter
Output Frequency
Output Skew: NOTE 1, 2
156.25MHz, Integration Range:
1.875MHz – 20MHz
tjit(Ø)
RMS Phase Jitter (Random);
NOTE 3
125MHz, Integration Range:
1.875MHz – 20MHz
62.5MHz, Integration Range:
1.875MHz – 20MHz
t
R
/ t
F
odc
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
F_SEL[1:0] = 00, 01 or 11
F_SEL[1:0] = 10
200
43
49
0.48
0.59
0.53
700
57
51
Test Conditions
F_SEL[1:0] = 00
F_SEL[1:0] = 01 or 11
F_SEL[1:0] = 10
Minimum
140
112
56
Typical
156.25
125
62.5
Maximum
175
140
70
60
Units
MHz
MHz
MHz
MHz
ps
ps
ps
ps
%
%
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE 1: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at V
DDO
/2.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Please refer to the Phase Noise Plots.
Typical Phase Noise at 62.5MHz (3.3V)
62.5MHz
RMS Phase Jitter (Random)
1.875MHz to 20MHz = 0.55ps (typical)
dBc
Hz
Noise Power
Raw Phase Noise Data
Offset Frequency (Hz)
FEMTOCLOCK™ CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY
SYNTHESIZER
5
➝
Phase Noise Result by adding a
10Gb Ethernet filter to raw data
➝
10Gb Ethernet Filter
➝
Rev B 4/2/15
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