Freescale Semiconductor
Technical Data
Document Number: MM908E621
Rev. 6.0, 4/2012
Integrated Quad Half-bridge and
Triple High Side with Embedded
MCU and LIN for High End
Mirror
The 908E621 is an integrated single package solution that
includes a high performance HC08 microcontroller with a
SMARTMOS analog control IC. The HC08 includes flash memory, a
timer, enhanced serial communications interface (ESCI), a 10 bit
analog-to-digital converter (ADC), internal serial peripheral interface
(SPI), and an internal clock generator module (ICG). The analog
control die provides four half-bridge and three high side outputs with
diagnostic functions, a Hall effect sensor input, analog inputs, voltage
regulator, window watchdog, and local interconnect network (LIN)
physical layer.
The single package solution, together with LIN, provides optimal
application performance adjustments and space saving PCB design.
It is well-suited for the control of automotive high end mirrors.
Features
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High performance M68HC908EY16 core
16 KB of on-chip flash memory, 512 B of RAM
Two 16-bit, two-channel timers
LIN physical layer interface
Autonomous MCU watchdog / MCU supervision
One analog input with switchable current source
Four low R
DS(ON)
half-bridge outputs
Three low R
DS(ON)
high side outputs
Wake-up and 2 or 3-pin Hall effect sensor input
12 microcontroller I/Os
Pb-free packaging designated by suffix codes EK
908E621
QUAD HALF-BRIDGE AND TRIPLE HIGH SIDE
SWITCH WITH EMBEDDED MCU AND LIN
EK (Pb-Free)
98ASA10712D
54-PIN SOICW-EP
ORDERING INFORMATION
Device
(Add
an R2 suffix for
Tape and reel orders)
MM908E621ACPEK
Temperature
Range (T
A
)
-40 to 85°C
Package
54 SOICW-EP
VSP1:8]
LIN
VDDA/VREFH
EVDD
4.7
μF
VDD
100 nF
VSSA/VREFL
EVSS
VSS
RST A
RST
IRQ A
IRQ
PTA/KBD0
PTA1/KBD1
μC
PortA
PTA2/KBD2
PTA3/KBD3
PTA4/KBD4
PTB3/AD3
μC
PortB
PTB4/AD4
PTB5/AD5
PTC2/MCLK
μC
PortC
PTC3/OSC2
PTC4/OSC1
Internally Connected
PTD0/TACH0
μC
PortD
PTD1/TACH1
μC
PortE
Internally Connected
PTE1/RXD
L0
HB1
HB2
HB3
HB4
HS1
HS2
HS3
HVDD
A0
A0CST
H0
TESTMODE
EP
GND[1:4]
>22
μF
Wake-up Input
100 nF
M
M
M
High Side Output 1
High Side Output 2
High Side Output 3
Switched 5.0 V Output
Analog Input with Curet Source
Analog Input Current Source Trim
Two 3-pin Hall Sensor Input
Pull to GND for User Mode
4 x Half-brideOutputs
908E621
Figure 1. 908E621 Simplified Application Diagram
Freescale Semiconductor, Inc. reserves the right to change the detail specifications,
as may be required, to permit improvements in the design of its products.
© Freescale Semiconductor, Inc., 2007-2012. All rights reserved.
2
VSSA/VREFL
EVSS
IRQ
GND[1:4]
VSUP[1:8]
TESTMODE
RST_A
IRQ_A
PTD0/TACH0
PTE1/RXD
RST
LIN
Single Breakpoint
Break Module
Voltage
Regulator
PTE1/RXD
PTE0/TXD
TXD
LIN
Physical Layer
Wakeup Port
Reset
Control
High Side Driver
& Diagnostic
High Side Driver
& Diagnostic
High Side Driver
& Diagnostic
Switched VDD
Driver &
Diagnostic
RXD
5-Bit Keyboard
Interrupt Module
2-channel Timer
Interface Module A
2-channel Timer
Interface Module B
Enhanced Serial
Communication
Interface Module
Autonomous
Watchdog
Computer Operating
Properly Module
Serial Peripheral
Interface Module
Configuration
Register Module
Periodic Wake-up
Timebase Module
Arbiter Module
Prescaler Module
BEMF Module
PTC1/MOSI
PTA5/SPSCK
PTC0/MISO
MISO
MOSI
SPSCK
PTA6/SS
SS
SPI
&
CONTROL
PTD0/TACH0
PWM
VSS
VDD
HVDD
L0
HS1[a:b]
HS2
HS3
HB1
908E621
Internal Bus
24 Integral System
Integration Module
Single External
IRQ Module
Half Bridge
Driver &
Diagnostic
Half Bridge
Driver &
Diagnostic
HB2
EVDD
INTERNAL BLOCK DIAGRAM
VDDA/VREFH
M68HC08 CPU
CPU
ALU
Registers
PTA0/KBD0
Control and Status
Register, 64 Bytes
User Flash, 15,872 Bytes
User RAM, 512 Bytes
Monitor ROM, 310 Bytes
Flash programming
(Burn-in), ROM 1024 Bytes
PTA1/KBD1
User Flash Vector
Space, 36 Bytes
PTA2/KBD2
OSC2 Internal Clock
OSC1 Generator Module
PTA3/KBD3
RST
PTA4/KBD4
IRQ
PTB3/AD3
PTB4/AD4
PTB5/AD5
Power-ON
Reset Module
Security Module
VREFH
VDDA 10 Bit Analog-to-
VREFL Digital Converter
Module
VSSA
VDD
POWER
VSS
INTERNAL BLOCK DIAGRAM
HB3
PTC2/MCLK
Half Bridge
Driver &
Diagnostic
PTC3/OSC2
Half Bridge
Driver &
Diagnostic
HB4
PORT C
DDRC
DDRA
PORT A
PTC4/OSC1
PTD1/TACH1
PTD1/TACH1
PTD0/TACH0
PTE1/RXD
PTE0/TXD
PTC4/OSC1
PTC3/OSC2
PTC2/MCLK
PTC1/MOSI
PTC0/MISO
FLSVPP
HALLPORT
PTB0/AD0
ADOUT
Analog
Multiplexer
H0
A0
A0CST
Analog Port
with Current
Source
PORT D PORT E
DDRD
DDRE
DDRB
PORT B
PTA6/SS
PTA5/SPSCK
PTA4/KBD4
PTA3/KBD3
PTA2/KBD2
PTA1/KBD1
PTA0/KBD0
PTB7/AD7/TBCH1
PTB6/AD6/TBCH0
PTB5/AD5
PTB4/AD4
PTB3/AD3
PTB2/AD2
PTB0/AD0
PTB0/AD0
Analog Integrated Circuit Device Data
Freescale Semiconductor
Figure 2. 908E621 Simplified Internal Block Diagram
PIN CONNECTIONS
PIN CONNECTIONS
Transparent Top
View of Package
PTC4/OSC1
PTC3/OSC2
PTC2/MCLK
PTB5/AD5
PTB4/AD4
PTB3/AD3
IRQ
RST
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
(PTD0/TACH0/BEMF -> PWM)
PTD1/TACH1
RST_A
IRQ_A
LIN
A0CST
A0
GND1
HB4
VSUP1
GND2
HB3
VSUP2
NC
NC
TESTMODE
GND3
HB2
VSUP3
Exposed
Pad
41
40
39
38
37
36
35
34
33
32
31
30
29
28
PTA0/KBD0
PTA1/KBD1
PTA2/KBD2
FLSVPP
PTA3/KBD3
PTA4/KBD4
VDDA/VREFH
EVDD
EVSS
VSSA/VREFL
(PTE1/RXD <- RXD)
VSS
VDD
HVDD
L0
H0
HS3
VSUP8
HS2
VSUP7
HS1b
HS1a
VSUP6
VSUP5
GND4
HB1
VSUP4
Figure 3. Pin Connections
Table 1. Pin Definitions
A functional description of each pin can be found in the
Functional Pin Description
section beginning on page
19.
Die
MCU
Pin
1
2
3
4
5
6
7
8
9
Pin Name
PTC4/OSC1
PTC3/OSC2
PTC2/MCLK
PTB5/AD5
PTB4/AD4
PTB3/AD3
IRQ
RST
Formal Name
Port C I/Os
Definition
These pins are special function, bidirectional I/O port pins that are
shared with other functional modules in the MCU.
These pins are special function, bidirectional I/O port pins that are
shared with other functional modules in the MCU.
This pin is an asynchronous external interrupt input pin.
This pin is bidirectional, allowing a reset of the entire system. It is driven
low when any internal reset source is asserted.
This pin is the PWM signal test pin. It internally connects the MCU
PTD0/TACH0 pin with the Analog die PWM input.
Note: Do not connect in the application.
MCU
Port B I/Os
MCU
MCU
MCU /
Analog
External Interrupt
Input
External Reset
PWM signal
(PTD0/TACH0/BEMF
-> PWM)
MCU
MCU /
Analog
10
44
PTD1/TACH1
(PTE1/RXD <- RXD)
Port D I/Os
LIN Transceiver
Output
This pin is a special function, bidirectional I/O port pin that is shared with
other functional modules in the MCU.
This pin is the LIN Transceiver output test pin. It internally connects the
MCU PTE1/RXD pin with the Analog die LIN transceiver output pin
RXD.
Note: Do not connect in the application.
908E621
Analog Integrated Circuit Device Data
Freescale Semiconductor
3
PIN CONNECTIONS
Table 1. Pin Definitions (continued)
A functional description of each pin can be found in the
Functional Pin Description
section beginning on page
19.
Die
MCU
MCU
MCU
Pin
45
48
46
47
49
50
52
53
54
51
11
12
13
14
15
16
19
25
30
29
26
20
17
18
21
27
28
31
32
35
22
23
24
34
35
36
38
Analog
39
Pin Name
VSSA/VREFL
VDDA/VREFH
EVSS
EVDD
PTA4/KBD4
PTA3/KBD3
PTA2/KBD2
PTA1/KBD1
PTA0/KBD0
FLSVPP
RST_A
IRQ_A
Formal Name
ADC Supply and
Reference Pins
MCU Power Supply
Pins
Port A I/Os
Definition
These pins are the power supply and voltage reference pins for the
analog-to-digital converter (ADC).
These pins are the ground and power supply pins, respectively. The
MCU operates from a single power supply.
These pins are special function, bidirectional I/O port pins that are
shared with other functional modules in the MCU.
MCU
Analog
Analog
Analog
Analog
Analog
Analog
Test Pin
Internal Reset
Internal Interrupt
Output
LIN Bus
Analog Input Trim Pin
Analog Input Pin
Power Ground Pins
For test purposes only. Do not connect in the application.
This pin is the bidirectional reset pin of the analog die.
This pin is the interrupt output pin of the analog die indicating errors or
wake-up events.
This pin represents the single wire bus transmitter and receiver.
This is the analog input trim pin for the A0 input. This is to connect a
known fixed resistor value to trim the current source measurement.
This pin is an analog input port with selectable source values.
These pins are device power ground connections.
LIN
A0CST
A0
GND1
GND2
GND3
GND4
HB1
HB2
HB3
HB4
VSUP1
VSUP2
VSUP3
VSUP4
VSUP5
VSUP6
VSUP7
NC
NC
TESTMODE
HS1a
HS1b
HS2
HS3
H0
Analog
Half-bridge Outputs
This device includes power MOSFETs configured as four half-bridge
driver outputs. These outputs may be configured for DC motor drivers,
or as high side and low side switches.
Note: The HB3 and HB4 have a lower R
DS(ON)
then HB1 and HB2.
Analog
Power Supply Pins
These pins are device power supply pins.
–
Analog
Analog
Analog
No Connect
TESTMODE Input
These pins are not connected.
Pin for test purpose only. In application this pin needs to be tied GND.
High Side HS1 Output This output pin is a low R
DS(ON)
high side switch.
High Side HS2 Output These output pins are low R
DS(ON)
high side switches.
High Side HS3 Output
Hall-Effect Sensor /
General Purpose
Input
Wake-up Input
Switchable V
DD
Output
Voltage Regulator
Output
This pin provides an input for a Hall-effect sensor or general purpose
input.
This pin provides an high voltage input, which is wake-up capable.
This pin is a switchable V
DD
output for driving resistive loads requiring
a regulated 5.0 V supply; e.g. potentiometers.
The +5. V voltage regulator output pin is intended to supply the
embedded microcontroller.
Analog
Analog
Analog
40
41
42
L0
HVDD
VDD
908E621
4
Analog Integrated Circuit Device Data
Freescale Semiconductor
PIN CONNECTIONS
Table 1. Pin Definitions (continued)
A functional description of each pin can be found in the
Functional Pin Description
section beginning on page
19.
Die
Analog
–
Pin
43
EP
Pin Name
VSS
Exposed Pad
Formal Name
Voltage Regulator
Ground
Exposed Pad
Definition
Ground pin for the connection of all non-power ground connections
(microcontroller and sensors).
The exposed pad pin on the bottom side of the package conducts heat
from the chip to the PCB board.
908E621
Analog Integrated Circuit Device Data
Freescale Semiconductor
5
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