CAV24C32
32-Kb I
2
C CMOS Serial
EEPROM
Description
The CAV24C32 is a 32−Kb CMOS Serial EEPROM devices,
internally organized as 4096 words of 8 bits each.
It features a 32−byte page write buffer and supports the Standard
(100 kHz) and Fast (400 kHz) I
2
C protocol.
External address pins make it possible to address up to eight
CAV24C32 devices on the same bus.
Features
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WLCSP5
C5A SUFFIX
CASE 567JQ
WLCSP4
C4C SUFFIX
CASE 567JY
SOIC−8
W SUFFIX
CASE 751BD
Automotive Temperature Grade 1 (−40°C to +125°C)
Supports Standard and Fast I
2
C Protocol
2.5 V to 5.5 V Supply Voltage Range
32−Byte Page Write Buffer
Hardware Write Protection for Entire Memory
CAV Prefix for Automotive and Other Applications Requiring Site
and Change Control
Schmitt Triggers and Noise Suppression Filters on I
2
C Bus Inputs
(SCL and SDA)
Low Power CMOS Technology
1,000,000 Program/Erase Cycles
100 Year Data Retention
SOIC, TSSOP 8−lead, and WLCSP 4−Ball and 5−Ball Packages
This Device is Pb−Free, Halogen Free/BFR Free, and RoHS
Compliant
V
CC
TSSOP−8
Y SUFFIX
CASE 948AL
PIN CONFIGURATIONS
(Top Views)
1
1
V
CC
2
A
V
SS
A
V
CC
V
SS
B
SCL
SDA
B
SDA
C
WP
SCL
2
3
WLCSP4 (C4C)
WLCSP5 (C5A)
1
A
0
A
1
A
2
V
CC
WP
SCL
SDA
SOIC (W), TSSOP (Y)
SCL
V
SS
CAV24C32
SDA
A
2
, A
1
, A
0
WP
For the location of Pin 1, please consult the
corresponding package drawing.
PIN FUNCTION
V
SS
Pin Name
A0, A1, A2
SDA
SCL
WP
V
CC
V
SS
This document contains information on some products that are still under development.
ON Semiconductor reserves the right to change or discontinue these products without
notice.
Function
Device Address Input
Serial Data Input/Output
Serial Clock Input
Write Protect Input
Power Supply
Ground
Figure 1. Functional Symbol
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 12 of this data sheet.
©
Semiconductor Components Industries, LLC, 2017
1
March, 2017 − Rev. 3
Publication Order Number:
CAV24C32/D
CAV24C32
DEVICE MARKINGS
(TSSOP−8)
(SOIC−8)
C32F
AYMXXX
G
C32F
A
Y
M
XXX
G
= Specific Device Code
= Assembly Location
= Production Year (Last Digit)
= Production Month (1-9, O, N, D)
= Last Three Digits of Assembly Lot Number
= Pb−Free Package
24C32F
AYMXXX
G
24C32F
A
Y
M
XXX
G
= Specific Device Code
= Assembly Location
= Production Year (Last Digit)
= Production Month (1-9, O, N, D)
= Last Three Digits of Assembly Lot Number
= Pb−Free Package
(WLCSP−4)
B
YW
(WLCSP−5)
2
YW
2
= Specific Device Code
YW = Production Date Code
B
= Specific Device Code
YW = Production Date Code
Table 1. ABSOLUTE MAXIMUM RATINGS
Parameters
Storage Temperature
Voltage on any Pin with Respect to Ground (Note 1)
Ratings
–65 to +150
–0.5 to +6.5
Units
°C
V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. During input transitions, voltage undershoot on any pin should not exceed −1 V for more than 20 ns. Voltage overshoot on pins A
0
, A
1
, A
2
and WP should not exceed V
CC
+ 1 V for more than 20 ns, while voltage on the I
2
C bus pins, SCL and SDA, should not exceed the absolute
maximum ratings, irrespective of V
CC
.
Table 2. RELIABILITY CHARACTERISTICS
(Note 2)
Symbol
N
END
(Note 3)
T
DR
Endurance
Data Retention
Parameter
Min
1,000,000
100
Units
Program/Erase Cycles
Years
2. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
3. Page Mode, V
CC
= 5 V, 25°C.
Table 3. D.C. OPERATING CHARACTERISTICS
(
V
CC
= 2.5 V to 5.5 V, T
A
= −40°C to +125°C, unless otherwise specified.)
Symbol
I
CCR
I
CCW
I
SB
I
L
V
IL
V
IH
Parameter
Read Current
Write Current
Standby Current
I/O Pin Leakage
Input Low Voltage
Input High Voltage
A
0
, A
1
, A
2
and WP
SCL and SDA
V
OL
Output Low Voltage
V
CC
> 2.5 V, I
OL
= 3 mA
Test Conditions
Read, f
SCL
= 400 kHz
Write, f
SCL
= 400 kHz
All I/O Pins at GND or V
CC
Pin at GND or V
CC
−0.5
0.7 x V
CC
0.7 x V
CC
T
A
= −40°C to +125°C
Min
Max
1
2
5
2
0.3 x V
CC
V
CC
+ 0.5
5.5
0.4
V
Units
mA
mA
mA
mA
V
V
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
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CAV24C32
Table 4. PIN IMPEDANCE CHARACTERISTICS
(V
CC
= 2.5 V to 5.5 V, T
A
= −40°C to +125°C, unless otherwise specified.)
Symbol
C
IN
(Note 4)
C
IN
(Note 4)
I
WP
(Note 5)
Parameter
SDA I/O Pin Capacitance
Input Capacitance (other pins)
WP Input Current
Conditions
V
IN
= 0 V, T
A
= 25°C, V
CC
= 5.0 V
V
IN
= 0 V, T
A
= 25°C, V
CC
= 5.0 V
V
IN
< V
IH
, V
CC
= 5.5 V
V
IN
< V
IH
, V
CC
= 3.3 V
V
IN
< V
IH
, V
CC
= 2.5 V
V
IN
< V
IH
I
A
(Note 5)
Address Input Current
(A0, A1, A2)
Product Rev F
V
IN
< V
IH
, V
CC
= 5.5 V
V
IN
< V
IH
, V
CC
= 3.3 V
V
IN
< V
IH
, V
CC
= 2.5 V
V
IN
> V
IH
Max
8
6
130
120
80
2
50
35
25
2
mA
Units
pF
pF
mA
4. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
5. When not driven, the WP, A0, A1 and A2 pins are pulled down to GND internally. For improved noise immunity, the internal pull−down is relatively
strong; therefore the external driver must be able to supply the pull−down current when attempting to drive the input HIGH. To conserve power,
as the input level exceeds the trip point of the CMOS input buffer (~ 0.5 x V
CC
), the strong pull−down reverts to a weak current source.
Table 5. A.C. CHARACTERISTICS
(V
CC
= 2.5 V to 5.5 V, T
A
= −40°C to +125°C, unless otherwise specified.) (Note 6)
Standard
Symbol
F
SCL
t
HD:STA
t
LOW
t
HIGH
t
SU:STA
t
HD:DAT
t
SU:DAT
t
R
t
F
(Note 6)
t
SU:STO
t
BUF
t
AA
t
DH
T
i
(Note 6)
t
SU:WP
t
HD:WP
t
WR
t
PU
(Notes 7, 8)
Clock Frequency
START Condition Hold Time
Low Period of SCL Clock
High Period of SCL Clock
START Condition Setup Time
Data In Hold Time
Data In Setup Time
SDA and SCL Rise Time
SDA and SCL Fall Time
STOP Condition Setup Time
Bus Free Time Between STOP and START
SCL Low to Data Out Valid
Data Out Hold Time
Noise Pulse Filtered at SCL and SDA Inputs
WP Setup Time
WP Hold Time
Write Cycle Time
Power−up to Ready Mode
0
2.5
5
1
100
100
0
2.5
5
1
4
4.7
3.5
100
100
4
4.7
4
4.7
0
250
1000
300
0.6
1.3
0.9
Parameter
Min
Max
100
0.6
1.3
0.6
0.6
0
100
300
300
Min
Fast
Max
400
Units
kHz
ms
ms
ms
ms
ms
ns
ns
ns
ms
ms
ms
ns
ns
ms
ms
ms
ms
6. Test conditions according to “AC Test Conditions” table.
7. Tested initially and after a design or process change that affects this parameter.
8. t
PU
is the delay between the time V
CC
is stable and the device is ready to accept commands.
Table 6. A.C. TEST CONDITIONS
Input Drive Levels
Input Rise and Fall Time
Input Reference Levels
Output Reference Level
Output Test Load
0.2 x V
CC
to 0.8 x V
CC
≤
50 ns
0.3 x V
CC
, 0.7 x V
CC
0.5 x V
CC
Current Source I
OL
= 3 mA; C
L
= 100 pF
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CAV24C32
Power-On Reset (POR)
Each CAV24C32 incorporates Power-On Reset (POR)
circuitry which protects the internal logic against powering
up in the wrong state. The device will power up into Standby
mode after V
CC
exceeds the POR trigger level and will
power down into Reset mode when V
CC
drops below the
POR trigger level. This bi-directional POR behavior
protects the device against ‘brown-out’ failure following a
temporary loss of power.
Pin Description
SCL:
The Serial Clock input pin accepts the clock signal
generated by the Master.
SDA:
The Serial Data I/O pin accepts input data and delivers
output data. In transmit mode, this pin is open drain. Data is
acquired on the positive edge, and is delivered on the
negative edge of SCL.
A
0
, A
1
and A
2
:
The Address inputs set the device address
that must be matched by the corresponding Slave address
bits. The Address inputs are hard-wired HIGH or LOW
allowing for up to eight devices to be used (cascaded) on the
same bus. When left floating, these pins are pulled LOW
internally.
WP:
When pulled HIGH, the Write Protect input pin
inhibits all write operations. When left floating, this pin is
pulled LOW internally.
Functional Description
The CAV24C32 supports the Inter-Integrated Circuit
2
C) Bus protocol. The protocol relies on the use of a Master
(I
device, which provides the clock and directs bus traffic, and
Slave devices which execute requests. The CAV24C32
operates as a Slave device. Both Master and Slave can
transmit or receive, but only the Master can assign those
roles.
I
2
C Bus Protocol
The 2-wire I
2
C bus consists of two lines, SCL and SDA,
connected to the V
CC
supply via pull-up resistors. The
Master provides the clock to the SCL line, and either the
Master or the Slaves drive the SDA line. A ‘0’ is transmitted
by pulling a line LOW and a ‘1’ by letting it stay HIGH. Data
transfer may be initiated only when the bus is not busy (see
A.C. Characteristics). During data transfer, SDA must
remain stable while SCL is HIGH.
START/STOP Condition
An SDA transition while SCL is HIGH creates a START
or STOP condition (Figure 2). The START consists of a
HIGH to LOW SDA transition, while SCL is HIGH. Absent
the START, a Slave will not respond to the Master. The
STOP completes all commands, and consists of a LOW to
HIGH SDA transition, while SCL is HIGH.
Device Addressing
The Master addresses a Slave by creating a START
condition and then broadcasting an 8-bit Slave address. For
the CAV24C32, the first four bits of the Slave address are set
to 1010 (Ah); the next three bits, A
2
, A
1
and A
0
, must match
the logic state of the similarly named input pins. The R/W
bit tells the Slave whether the Master intends to read (1) or
write (0) data (Figure 3).
Acknowledge
During the 9
th
clock cycle following every byte sent to the
bus, the transmitter releases the SDA line, allowing the
receiver to respond. The receiver then either acknowledges
(ACK) by pulling SDA LOW, or does not acknowledge
(NoACK) by letting SDA stay HIGH (Figure 4). Bus timing
is illustrated in Figure 5.
SCL
SDA
START
CONDITION
STOP
CONDITION
Figure 2. Start/Stop Timing
1
0
1
0
A
2
A
1
A
0
R/W
DEVICE ADDRESS
Figure 3. Slave Address Bits
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CAV24C32
BUS RELEASE DELAY (TRANSMITTER)
SCL FROM
MASTER
1
8
9
BUS RELEASE DELAY (RECEIVER)
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
START
ACK DELAY (≤ t
AA
)
ACK SETUP (≥ t
SU:DAT
)
Figure 4. Acknowledge Timing
t
F
t
LOW
SCL
t
SU:STA
t
HD:SDA
SDA IN
t
AA
SDA OUT
t
HIGH
t
LOW
t
R
t
HD:DAT
t
SU:DAT
t
SU:STO
t
DH
t
BUF
Figure 5. Bus Timing
WRITE OPERATIONS
Byte Write
Acknowledge Polling
To write data to memory, the Master creates a START
condition on the bus and then broadcasts a Slave address
with the R/W bit set to ‘0’. The Master then sends two
address bytes and a data byte and concludes the session by
creating a STOP condition on the bus. The Slave responds
with ACK after every byte sent by the Master (Figure 6). The
STOP starts the internal Write cycle, and while this
operation is in progress (t
WR
), the SDA output is tri-stated
and the Slave does not acknowledge the Master (Figure 7).
Page Write
As soon (and as long) as internal Write is in progress, the
Slave will not acknowledge the Master. This feature enables
the Master to immediately follow-up with a new Read or
Write request, rather than wait for the maximum specified
Write time (t
WR
) to elapse. Upon receiving a NoACK
response from the Slave, the Master simply repeats the
request until the Slave responds with ACK.
Hardware Write Protection
The Byte Write operation can be expanded to Page Write,
by sending more than one data byte to the Slave before
issuing the STOP condition (Figure 8). Up to 32 distinct data
bytes can be loaded into the internal Page Write Buffer
starting at the address provided by the Master. The page
address is latched, and as long as the Master keeps sending
data, the internal byte address is incremented up to the end
of page, where it then wraps around (within the page). New
data can therefore replace data loaded earlier. Following the
STOP, data loaded during the Page Write session will be
written to memory in a single internal Write cycle (t
WR
).
With the WP pin held HIGH, the entire memory is
protected against Write operations. If the WP pin is left
floating or is grounded, it has no impact on the Write
operation. The state of the WP pin is strobed on the last
falling edge of SCL immediately preceding the 1
st
data byte
(Figure 9). If the WP pin is HIGH during the strobe interval,
the Slave will not acknowledge the data byte and the Write
request will be rejected.
Delivery State
The CAV24C32 is shipped erased, i.e., all bytes are FFh.
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