The CY25200 is a Spread Spectrum Clock Generator (SSCG) IC
used to reduce Electro Magnetic Interference (EMI) found in
today’s high speed digital electronic systems.
The device uses a Cypress proprietary Phase-Locked Loop
(PLL) and Spread Spectrum Clock (SSC) technology to
synthesize and modulate the frequency of the input clock. By
frequency modulating the clock, the measured EMI at the
fundamental and harmonic frequencies are reduced. This
reduction in radiated energy significantly reduces the cost of
complying with regulatory agency requirements (EMC) and
improves time to market, without degrading system
performance.
The CY25200 uses a factory and field-programmable
configuration memory array to synthesize output frequency,
Table 1. Pin Summary
Name
XIN
XOUT
VDD
AVDD
VSS
AVSS
VDDL
VSSL
SSCLK1
SSCLK2
SSCLK3
SSCLK4
SSCLK5/REFOUT/CP2
SSCLK6/REFOUT/CP3
CP0
[1]
CP1
[1]
Pin Number
1
16
2
3
13
5
11
6
7
8
9
12
14
15
4
10
spread %, crystal load capacitor, clock control pins, PD#, and OE
options.
The spread % is factory and field-programmed to either center
spread or down spread with various spread percentages. The
range for center spread is from ±0.25% to ±2.50%. The range for
down spread is from –0.5% to –5.0%. Contact the factory for
smaller or larger spread % amounts, if required.
The input to the CY25200 is either a crystal or a clock signal. The
input frequency range for crystals is 8 to 30 MHz and for clock
signals is 8 to 166 MHz.
The CY25200 has six clock outputs, SSCLK1 to SSCLK6. The
frequency modulated SSCLK outputs are programmed from 3 to
200 MHz.
The CY25200 products are available in a 16-pin TSSOP
package with a commercial operating temperature range of 0 to
70
C.
Description
Crystal input or Reference Clock input
Crystal output. Leave this pin floating if external clock is used
3.3 V power supply for digital logic and SSCLK5 and 6 clock outputs
3.3 V analog–PLL power supply
Ground
Analog ground
2.5 V or 3.3 V power supply for SSCLK1/2/3/4 clock outputs
VDDL power supply ground
Programmable spread spectrum clock output at VDDL level (2.5 V or 3.3 V)
Programmable spread spectrum clock output at VDDL level (2.5 V or 3.3 V)
Programmable spread spectrum clock output at VDDL level (2.5 V or 3.3 V)
Programmable spread spectrum clock output at VDDL level (2.5 V or 3.3 V)
Programmable spread spectrum clock or buffered reference output at VDD
level (3.3 V) or control pin, CP2
Programmable spread spectrum clock or buffered reference output at VDD
level (3.3 V) or control pin, CP3
Control pin 0
Control pin 1
Note
1. Pins are programmed to be any of the following control signals: OE: Output Enable, OE = 1, all the SSCLK outputs are enabled; PD#: Power down, PD# = 0, all the
SSCLK outputs are three-stated and the part enters a low power state; SSON: Spread Spectrum Control (SSON = 0, No Spread and SSON = 1, Spread Signal),
CLKSEL: SSCLK Output Frequency Select.See
Control Pins (CP0, CP1, CP2 and CP3)
for control pins programming options.
Document Number: 38-07633 Rev. *H
Page 3 of 15
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CY25200
Table 2. Fixed Function Pins
Pin Function
Pin Name
Pin#
Units
Program Value
CLKSEL = 0
Program Value
CLKSEL = 1
Output Clock Frequency
SSCLK[1:6]
7, 8, 9, 12, 14, 15
MHz
USER SPECIFIED
USER SPECIFIED
Input Frequency
XIN and XOUT
1 and 16
MHz
C
XIN
and C
XOUT
XIN and XOUT
1 and 16
pF
Spread Percent
SSCLK[1:6]
7, 8, 9, 12, 14, 15
% and Center- or
Down-spread
USER SPECIFIED
Modulation
Frequency
SSCLK[1:6]
7, 8, 9, 12, 14, 15
kHz
USER SPECIFIED USER SPECIFIED
USER SPECIFIED
Table 3. Multi-Function Pins
Pin
Function
Pin Name
Pin#
Units
Output Clock/REFOUT/OE/SSON/CLKSEL
SSCLK5/REFOUT/CP2
14
Function
USER SPECIFIED
SSCLK6/REFOUT/CP3
15
Function
USER SPECIFIED
4
Function
USER SPECIFIED
OE/PD#/SSON/CLKSEL
CP0
CP1
10
Function
USER SPECIFIED
Programming Description
Field-Programmable CY25200
The CY25200 is programmed at the package level, and must be
programmed prior to installation on a circuit board. Field
programmable devices are denoted by an “F” in the ordering
code, and are blank when shipped. The CY25200 is Flash
technology based, which allows it to be reprogrammed up to 100
times. This allows for fast and easy design changes and product
updates, and eliminates issues with old and out of date inventory.
Samples and small prototype quantities are programmed on the
CY3672 programmer with the CY3695 socket adapter.
industry standard JEDEC file used for programming the
CY25200.
CyberClocks
Online
is
available
at
www.cyberclocksonline.com
website.
Factory-Programmed CY25200
Factory programming by Cypress is available for high volume
orders. All requests must be submitted to the local Cypress Field
Application Engineer (FAE) or sales representative. After the
request is processed, you will receive a new part number,
samples, and data sheet with the programmed values. This part
number is used for additional sample requests and production
orders.
CyberClocks Online Software
CyberClocks Online Software is a web based software
application that allows the user to custom configure the
CY25200. All the parameters in
Table 2
and
Table 3
are entered
as variables into the software. CyberClocks Online outputs an
Document Number: 38-07633 Rev. *H
Page 4 of 15
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CY25200
Product Functions
Control Pins (CP0, CP1, CP2 and CP3)
Four control signals are available through programming of pins
4, 10, 14, and 15.
CP0 (pin 4) and CP1 (pin10) are specifically designed to function
as control pins. However, pins 14 (SSCLK5/REFOUT/CP2) and
15 (SSCLK6/REFOUT/CP3) are multi-functional and can be
programmed to be either a control signal or an output clock
(SSCLK or REFOUT). All of the control pins, CP0, CP1, CP2,
and CP3 are programmable to one of the following functions:
■
■
■
■
CLKSEL
The CLKSEL control pin enables you to select between two
different SSCLK output frequencies. These must be related
frequencies that are derived off of a common PLL frequency.
Specifically, CLKSEL does not change the PLL frequency. It only
changes the output divider. For instance, 33.333 MHz and
66.666 MHz are both derived from a PLL frequency of 400 MHz,
by dividing it down by 12 and 6 respectively.
Table 4 on page 6
shows an example of how this is implemented. The PLL
frequency range is 100 to 400 MHz. The two output dividers in
the CY25200 can be any integer between 2 and 130, providing
two different but related frequencies as explained above.
Table 4 on page 6
and
Figure 3 on page 6
show an example
configuration using the frequencies just described. In this
example, the configurable pins SSCLK5 (pin 14) and SSCLK6
(pin 15) are used as output clocks.
OE (Output Enable): if OE = 1, all SSCLK and REFOUT outputs
are enabled.
SSON (Spread spectrum control): if SSON = 1, spread is on;
if SSON = 0, spread is off.
CLKSEL (Clock select): frequency select for all SSCLK outputs.
PD# (Power Down; active low): if PD# = 0, all the outputs are
three-stated and the part enters a low power state.
Input Frequency (XIN, Pin 1 and XOUT, Pin 16)
The input to the CY25200 is a crystal or a clock. The input
frequency range for crystals is 8 to 30 MHz, and for clock signal
is 8 to 166 MHz.
Note that the PD# function is available only on CP0 or CP1; it is
not available on CP2 or CP3.
C
XIN
and C
XOUT
(Pin 1 and Pin 16)
The CY25200 has internal load capacitors at pin 1 (C
XIN
) and
pin 16 (C
XOUT
). C
XIN
always equals C
XOUT
, and they are
programmable from 12 pF to 60 pF, in 0.5 pF increments. This
feature eliminates the need for external crystal load capacitors.
The following formula is used to calculate the value of C
XIN
and
C
XOUT
for matching the crystal load (C
L
):
C
XIN
= C
XOUT
= 2C
L
– C
P
Where C
L
is the crystal load capacitor as specified by the crystal
manufacturer and C
P
is the parasitic PCB capacitance on each
node of the crystal.
For example, if a crystal with C
L
of 16 pF is used, and C
P
is 2 pF,
C
XIN
and C
XOUT
is calculated as:
C
XIN
= C
XOUT
= (2 × 16) – 2 = 30 pF.
If using a driven reference clock, set C
XIN
and C
XOUT
to the
minimum value 12 pF, connect the reference to XIN/CLKIN, and
leave XOUT unconnected.
Example
Here is an example with three control pins:
■
■
■
■
■
■
CLKIN = 33 MHz
SSCLK1/2/3/4 = 100 MHz with ±1% spread
SSCLK 5 = REFOUT(33 MHz)
CP0 (pin 4) = PD#
CP1 (pin 10) = OE
CP3 (pin 15) = SSON
Figure 2. Example Pin Diagram
33.0MHz
VDD
AVDD
PD#
AVSS
VSSL
100MHz
100MHz
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
NC
SSON
REFOUT(33.0MHz)
VSS
100MHz
VDDL
OE
100MHz
The pinout for the above example is shown in
Figure 2.
Output Frequency (SSCLK1 through SSCLK6
Outputs)
All the SSCLK outputs are produced by synthesizing the input
reference frequency using a PLL and modulating the VCO
frequency. SSCLK[1:4] are fixed function output clocks (SSCLK).
SSCLK5 and SSCLK6 are also programmable to function the
same as SSCLK[1:4], or as buffered copies of the input reference
(REFOUT), or as control pin as discussed in
Control Pins (CP0,
CP1, CP2 and CP3).
To use the 2.5 V output drive option on
SSCLK[1:4], VDDL must be connected to a 2.5 V power supply
(SSCLK[1:4] outputs are powered by VDDL). When using the
2.5 V output drive option, the maximum output frequency on
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