73M1903
Modem Analog Front End
Simplifying System Integration
TM
DATA SHEET
March 2010
DESCRIPTION
The Teridian 73M1903 Analog Front End (AFE) IC
includes fully differential hybrid driver outputs, which
connect to the telephone line interface through a
transformer-based DAA. The receive pins are also
fully differential for maximum flexibility and
performance. This arrangement allows for the
design of a high performance hybrid circuit to
improve signal to noise performance under low
receive level conditions, and compatibility with any
standard transformer intended for PSTN
communications applications.
The device incorporates a programmable sample
rate circuit to support soft modem and DSP based
implementations of all speeds up to V.92 (56 kbps).
The sampling rates supported are from 7.2 kHz to
14.4 kHz by programming pre-scaler NCO and PLL
NCO.
The 73M1903 device incorporates a digital host
interface that is compatible with the serial ports
found on most commercially available DSPs and
processors and exchanges both payload and control
information with the host.
Cost-saving features of the device include an input
reference frequency circuit, which accepts a range
of crystals from 9-27 MHz. It also accepts external
reference clock values between 9-40 MHz
generated by the host processor. In most
applications, this eliminates the need for a dedicated
crystal oscillator and reduces the bill of material
(BOM).
The 73M1903 also supports two analog loop back
and one digital loop back test modes.
VBG
(HYBRID)
TXAP
TXAN
FEATURES
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Up to 56 kbps (V.92) performance
Programmable sample rates (7.2 - 14.4 kHz)
Reference clock range of 9-40 MHz
Crystal frequency range of 9-27 MHz
Host synchronous serial interface operation
Pin compatible with 73M2901CL/CE
modems
Low power modes
On board line interface drivers
Fully differential receiver and transmitter
Drivers for transformer interface
3.0 V – 3.6 V operation
5 V tolerant I/O
Industrial temperature range (-40 to +85
°C)
JATE compliant transmit spectrum
Package options:
•
32-pin QFN
•
20-pin TSSOP
RoHS compliant (6/6) lead-free packages
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APPLICATIONS
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Set Top Boxes
Personal Video Recorders (PVR)
Multifunction Peripherals (MFP)
Fax Machines
Internet Appliances
Game Consoles
Point of Sale Terminals
Automatic Teller Machines
Speaker Phones
RF Modems
Transmit
Drivers/
Filters
Receive
Mux/
Filters
DAA
Controls
Analog
Sigma
Delta
Ref.
SCLK
SDIN
RXAP
RXAN
DAC
Control
Registers
Serial
Port
SDOUT
FSB
GPIO
HOOK
Clocks
Control
Logic
Crystal
Rev. 2.1
© 2010 Teridian Semiconductor Corporation
1
73M1903 Data Sheet
DS_1903_032
Table of Contents
1
Signal Description ......................................................................................................................... 4
1.1 Serial Interface ........................................................................................................................ 5
2
Control and Status Registers ........................................................................................................ 8
2.1 GPIO .................................................................................................................................... 10
2.1.1 GPIO Data (GPIO): Address 02h .............................................................................. 10
2.1.2 GPIO Direction (DIR): Address 03h .......................................................................... 10
2.2 Analog I/O............................................................................................................................. 10
2.2.1 Control Register (CTRL 11): Address 0Bh ................................................................. 11
2.2.2 Control Register (CTRL 12): Address 0Ch ................................................................. 11
2.2.3 Control Register (CTRL 13): Address 0Dh ................................................................. 12
2.2.4 Control Register (CTRL 14): Address 0Eh ................................................................. 12
3
Clock Generation ......................................................................................................................... 13
3.1 Crystal Oscillator and Pre-scaler NCO................................................................................... 13
3.1.1 Control Register (CTRL 8): Address 08h.................................................................... 13
3.1.2 Control Register (CTRL 9): Address 09h.................................................................... 13
3.1.3 Control Register (CTRL 10): Address 0Ah ................................................................. 13
4
Modem Receiver .......................................................................................................................... 18
5
Modem Transmitter ..................................................................................................................... 21
5.1 Transmit Levels..................................................................................................................... 22
5.2 Transmit Power - dBm........................................................................................................... 23
5.3 Control Register (CTRL1): Address 00h ............................................................................... 23
5.4 Control Register (CTRL2): Address 01h ............................................................................... 24
5.5 Revision Register: Address 06h ............................................................................................ 24
6
Test Modes................................................................................................................................... 25
7
Power Saving Modes ................................................................................................................... 25
8
Electrical Specifications.............................................................................................................. 26
8.1 Absolute Maximum Ratings ................................................................................................... 26
8.2 Recommended Operating Conditions .................................................................................... 26
8.3 Digital Specifications ............................................................................................................. 27
8.3.1 DC Characteristics..................................................................................................... 27
8.3.2 AC Timing ................................................................................................................. 28
8.4 Analog Specifications ............................................................................................................ 29
8.4.1 DC Specifications ...................................................................................................... 29
8.4.2 AC Specifications ...................................................................................................... 29
8.5 Performance ......................................................................................................................... 30
8.5.1 Receiver .................................................................................................................... 30
8.5.2 Transmitter ................................................................................................................ 31
9
Pinouts ......................................................................................................................................... 33
9.1 32-Pin QFN Pinout ................................................................................................................ 33
9.2 20-Pin TSSOP Pinout ........................................................................................................... 34
10 Mechanical Specifications .......................................................................................................... 35
10.1 32-Pin QFN Mechanical Drawings ......................................................................................... 37
10.2 20-Pin TSSOP Mechanical Drawings .................................................................................... 38
11 Ordering Information ................................................................................................................... 39
Appendix A – 73M1903 DAA Resistor Calculation Guide .................................................................. 40
Appendix B – Crystal Oscillator.......................................................................................................... 42
Revision History .................................................................................................................................. 47
2
Rev. 2.1
DS_1903_032
73M1903 Data Sheet
Figures
Figure 1: Effect of the TYPE (FS mode) pin on
FS
with SckMode = 0....................................................... 7
Figure 2: Control Frame Position versus SPOS........................................................................................ 7
Figure 3: Serial Port Timing Diagram ....................................................................................................... 9
Figure 4: Analog Block Diagram............................................................................................................. 11
Figure 5: Clock Generation .................................................................................................................... 17
Figure 6: Overall Receiver Frequency Response ................................................................................... 19
Figure 7: Rx Passband Response.......................................................................................................... 19
Figure 8: RXD Spectrum of 1 kHz Tone ................................................................................................. 20
Figure 9: RXD Spectrum of 0.5 kHz, 1 kHz, 2 kHz, 3 kHz and 3.5 kHz Tones of Equal Amplitudes ......... 20
Figure 10: Frequency Response of TX Path for DC to 4 kHz in Band Signal........................................... 21
Figure 11: Serial Port Data Timing ......................................................................................................... 28
Figure 12: 32-Pin QFN Pinout ................................................................................................................ 33
Figure 13: 20-Pin TSSOP Pin out .......................................................................................................... 34
Figure 14: 73M1903 Schematic ............................................................................................................. 35
Figure 14: 32-Pin QFN Mechanical Specifications .................................................................................. 37
Figure 15: 20-Pin TSSOP Mechanical Specifications ............................................................................. 38
Figure 16: NCO Block Diagram.............................................................................................................. 42
Figure 17: PLL Block Diagram ............................................................................................................... 43
Tables
Table 1: Inputs Selected in Regular and Alternate Multiplexer Cycles ....................................................... 4
Table 2: Memory Map .............................................................................................................................. 8
Table 3: PLL Loop Filter Settings ........................................................................................................... 11
Table 4: Kvco versus Settings at Vc=1.6 V, 25 °C .................................................................................. 13
Table 5: PLL Power Down ..................................................................................................................... 14
Table 6: Examples of NCO Settings ....................................................................................................... 14
Table 7: Clock Generation Register Settings for Fxtal = 27 MHz ............................................................ 15
Table 8: Clock Generation Register Settings for Fxtal = 24.576 MHz...................................................... 16
Table 9: Clock Generation Register Settings for Fxtal = 9.216 MHz........................................................ 16
Table 10: Clock Generation Register Settings for Fxtal = 24.000 MHz.................................................... 17
Table 11: Clock Generation Register Settings for Fxtal = 25.35 MHz...................................................... 17
Table 12: Receive Gain ......................................................................................................................... 18
Table 13: Peak to RMS Ratios for Various Modulation Types ................................................................. 23
Table 14: Serial I/F Timing ..................................................................................................................... 28
Table 15: Reference Voltage Specifications ........................................................................................... 29
Table 16: Maximum Transmit Levels ...................................................................................................... 29
Table 17: Receiver Performance Specifications ..................................................................................... 30
Table 18: Transmitter Performance Specifications ................................................................................. 31
Table 19: 32-Pin QFN Pin Definitions..................................................................................................... 33
Table 20: 20-Pin TSSOP Pin Definitions ................................................................................................ 34
Table 21: Bill of Materials ....................................................................................................................... 36
Table 22: Ordering Information .............................................................................................................. 39
Rev. 2.1
3
73M1903 Data Sheet
DS_1903_032
1 Signal Description
The Teridian 73M1903 modem AFE IC is available in a 20-pin TSSOP or 32-pin QFN package with the
same pin out. The following table describes the function of each pin. There are two pairs of power
supply pins, VPA (analog) and VPD (digital). They should be decoupled separately from the supply
source in order to isolate digital noise from the analog circuits internal to the chip. Failure to adequately
isolate and decouple these supplies will compromise device performance.
Table 1: Inputs Selected in Regular and Alternate Multiplexer Cycles
Pin Name
VND
VNA
VPD
VPA
VPPLL
VNPLL
RST
OSCIN
OSCOUT
GPIO(0-7)
VREF
RXAP
RXAN
TXAP
TXAN
SCLK
SDOUT
SDIN
FS
TYPE
SckMode
Type
GND
GND
PWR
PWR
PWR
PWR
I
I
O
I/O
O
I
I
O
O
O
O
I
O
I
I
32QFN
Pin #
1,22
16
2,25
10
20
17
9
19
18
3, 4, 5, 6,
23,
24,30,31
13
15
14
12
11
8
32
29
7
27
28
20VT
Pin#
2,18
13
3
8
17
14
7
16
15
N/A
6
12
11
10
9
5
1
20
4
19
Description
Negative Digital Ground
Negative Analog Ground
Positive Digital Supply
Positive Analog Supply
Positive PLL Supply, shared with VPD
Negative PLL Ground
Master reset. When this pin is a logic 0 all registers are
reset to their default states; Weak-pulled high- default.
Crystal oscillator input. When providing an external clock
source, drive OSCIN.
Crystal oscillator circuit output pin.
Software definable digital input/output pins. Not available in
the 20VT (TSSOP) package.
Reference voltage pin (Reflects VREF).
Receive analog positive input.
Receive analog negative input.
Transmit analog positive output.
Transmit analog negative output.
Serial interface clock. With SCLK continuous selected,
Frequency = 256*Fs ( =2.4576 MHz for Fs=9.6 kHz)
Serial data output (or input to the host).
Serial data input (or output from the host).
Frame synchronization. (Active Low)
Type of frame sync. Open, weak-pulled high = early
(mode1); tied low = late (mode0).
Controls the SCLK behavior after
FS.
Open, weak-pulled
high = SCLK Continuous; tied low = 32 clocks per R/W
cycle. Not available in 20VT.
NA
4
Rev. 2.1
DS_1903_032
73M1903 Data Sheet
1.1
Serial Interface
The serial data port is a bi-directional port that is supported by many DSPs. Although the 73M1903 is a
peripheral to the DSP (host controller), the 73M1903 is the master of the serial port. It generates a serial
bit clock, Sclk, from a system clock, Sysclk, which is normally an output from an on-chip PLL that is
programmed by the user. The serial bit clock is derived by dividing the system clock by 18. The sclk rate,
Fsclk, is related to the frame synchronization rate, Fs, by the relationship Fsclk = 256 x Fs or Fs = Fsclk /
256 = Fsys / 18 / 256 = Fsys / 4608, where Fsys is the frequency of Sysclk. Fs is also the rate at which
both the transmit and receive data bytes are sent (received) to (by) the Host. Throughout this document
two pairs of sample rates, Fs, and crystal frequency, Fxtal, will be often cited to facilitate discussions.
They are:
1. Fxtal
1
= 27 MHz, Fs
1
= 7.2 kHz
2. Fxtal
2
= 18.432 MHz, Fs
2
= 8 kHz.
3. Fxtal
3
= 24.576 MHz, Fs
3
= 9.6 kHz – chip default.
Upon reset, until a switch to the PLL based clock, Pllclk, occurs, the system clock will be at the crystal
frequency, Fxtal, and therefore the serial bit clock will be Sclk = Fsys/18 = Fxtal/18.
Examples:
1. If Fxtal
1
= 27.000 MHz, then sclk=1.500 MHz and Fs=sclk/256 = 5.859375 kHz.
2. If Fxtal
2
= 18.432 MHz, then sclk=1.024 MHz and Fs=sclk/256 = 4.00 kHz.
3. If Fxtal
3
= 24.576 MHz, then sclk=1.3653 MHz and Fs=sclk/256 = 5.33 kHz.
When 73M1903 is programmed through the serial port to a desired Fs and the PLL has settled out, the
system clock will transition to the PLL-based clock in a glitch-less manner.
Examples:
1. If Fs
1
= 7.2 kHz, Fsys = 4608 * Fs = 33.1776 MHz and sclk = Fsys / 18 = 1.8432 MHz.
2. If Fs
2
= 8.0 kHz, Fsys = 4608 * Fs = 36.8640 MHz and sclk = Fsys / 18 = 2.048 MHz.
3. If Fs
3
= 9.6 kHz, Fsys = 4608 * Fs = 44.2368 MHz and sclk = Fsys / 18 = 2.4576 MHz.
This transition is entirely controlled by the host. Upon reset or power down of PLL and/or analog front
end, the chip will automatically run off the crystal until the host forces the transition by setting a bit in a
designated serial port register – location bit 7, 0Eh. The transition is forced on or after the second Frame
Synch period following the write to a designated PLL programming register (0Dh).
When reprogramming the PLL the host should first transition the system clock to the crystal before
reprogramming the PLL so that any transients associated with it will not adversely impact the serial port
communication.
Power saving is accomplished by disabling the analog front end by clearing bit 7 of CTRL1 (address 00h),
ENFE=0.
During the normal operation, a data
FS
is generated by the 73M1903 at the rate of Fs. For every data
FS
there are 16 bits transmitted and 16 bits received. The frame synchronization (FS) signal is pin
programmable for type.
FS
can either be early or late determined by the state of the TYPE input pin.
When the TYPE pin is left open, an early
FS
is generated in the bit clock prior to the first data bit
transmitted or received. When held low, a late FS operates as a chip select; the
FS
signal is active for all
bits that are transmitted or received. The TYPE input pin is sampled when the reset pin is active (low)
and ignored at all other times. The final state of the TYPE pin as the reset pin is de-asserted determines
the frame synchronization mode used.
Rev. 2.1
5
FPGA/CPLD
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