Integrated
Circuit
Systems, Inc.
ICS9212-13
Direct Rambus™ Clock Generator
General Description
The
ICS9212-13
is a High-speed clock generator providing
up to 600 MHz differential clock source for direct Rambus™
memory system. It includes DDLL (Distributed Delay
locked loop) and phase detection mechanism to
synchronize the direct Rambus™ channel clock to an
external system clock.
ICS9212-13
provides a solution for
a broad range of Direct Rambus memory applications. The
device works in conjunction with the ICS9250-09.
The
ICS9212-13
power management support system
turns “off” the Rambus™ channel clock to minimize power
consumption for mobile and other power–sensitive
applications. In “clock off” mode the device remains “on”
while the output is disabled, allowing fast transitions
between clock-off and clock–on states. In “power down”
mode it completely powers down for minimum power
dissipation.
The
ICS9212-13
meets the requirements for input frequency
tracking when the input frequency clock is using Spread
Spectrum clocking and also the optimum bandwidth is
maintained while attenuating the jitter of the reference
signal.
Features
•
•
•
•
•
Compatible with all Direct Rambus™ based IC s
Up to 600 MHz differential clock source for direct
Rambus™ memory system
Cycle to cycle jitter is less than 40ps
3.3 + 5% supply
Synchronization flexibility: Supports Systems that
need clock domains of Rambus channel to
synchronize with system or processor clock, or
systems that do not require synchronization of the
Rambus clock to another system clock
Excellent power management support
REFCLK input is from the ICS9250-09.
•
•
Block Diagram
BUSCLK_STOP#
PD#
FS(0:1)
Test MUX
GND
PLLclk
Refclk
B
Bypass MUX
Bypclk
Pin Configuration
VDDREF
REFCLK
VDD1
GND1
GND3
PCLK/M
SYNCLK/N
GND2
VDD2
VDDPD
BUSCLK_STOP#
PD#
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
FS0
FS1
VDD-OUT
GND-OUT
BUSCLKT
N/C
BUSCLKC
GND-OUT
VDD-OUT
MULTI0
MULTI1
FS2
PLL
A
Phase
Aligner
PAclk
GND
BUSCLKT
BUSCLKC
Multi(0:1)
Pclk/M
Synclk/N
Phase
Detector
2
24-Pin 150 Mil SSOP
0272F—08/08/07
ICS9212-13
ICS9212-13
Pin Descriptions
Pin #
1
2
3
4
5
6,7
8
9
10
11
12
14,15
16
17
18
19
20
21
22
13,23,24
Name
VDDREF
REFCLK
VDD1
GND1
GND3
PCLK/M, SYNCLK/N
GND2
VDD2
VDDPD
BUSCLK_ STOP#
PD#
MULTI (0:1)
VDD_OUT
GND_OUT
BUSCLKC
N/C
BUSCLKT
GND_OUT
VDD_OUT
FS(0:2)
Type
REFV
IN
PWR
PWR
PWR
IN
PWR
PWR
REFV
IN
IN
IN
PWR
PWR
OUT
N/C
OUT
PWR
PWR
IN
Description
Reference voltage for refclk, to be connected to CK133
Reference clock, to be connected to CK133
3.3 V power supply used for PLL
Ground for PLL
Ground for control inputs
Phase controller input, used to drive a phase aligner
that adjusts the phase of the busclk.
Ground for phase aligner
3.3 V power supply used for phase aligner
Reference voltage for phase detector inputs connected
to the controller
Active low output enable/disable
3.3V CMOS active low power down, the device is
powered down when the "(PD#) =0"
3.3V CMOS PLL Multiplier select, logic for selecting
the multiply ratio for the PLL from the input REFCLK
3.3V supply for clock out puts
Ground for clock outputs
Out put clock connected to the Rambus channel. This
output is the complement of BUSCLK
NOT USED
Output clock connected to the Rambus channel. This
output is the true component of BUSCLK
Ground for clock outputs
3.3V supply for clock out puts
3.3V CMOS Mode control, used in selecting bypass,
test, normal, and output test (OE)
0272F—08/08/07
2
ICS9212-13
PLL Divider Selection and PLL Values (PLLCLK = REFCLK*A/B)
Multo
0
0
1
1
Mult1
0
1
0
1
A
4
6
16
8
B
1
1
3
1
PLLCLK for REFCLK=50MHz
Reserved
300
266.7
400
PLLCLK for REFCLK=66.66MHz
266.6
400.0
355.5
533.3
Bypass and Test Mode Selection
Mode
Normal
Bypass
Test
Vendor Test A
Vendor Test B
Reserved
Output Test (OE)
FS0
0
1
1
0
1
1
0
FS1
0
0
1
0
0
1
1
FS2
0
0
0
1
1
1
X
Bypclk (int.)
Gnd
PLLclk
Refclk
-
-
-
-
BusClk
PAclk
PLLclk
Refclk
-
-
-
Hi-Z
BusClkB
PAclkB
PLLclkB
RefclkB
-
-
-
Hi-Z
Power Management Modes
State
NORMAL
Clk Off
Powerdown
PwrDnB
1
1
0
StopB
1
0
X
0272F—08/08/07
3
ICS9212-13
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . 4.0 V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to V
DD
+0.5 V
Ambient Operating Temperature . . . . . . . . . . 0°C to +70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Stresses above those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. These
ratings are stress specifications only and functional operation of the device at these or any other conditions above those
listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect product reliability.
Electrical Characteristics-input/supply/Outputs
Parameters
Supply Voltage
Refclk Input cycle time
Input cycle-to-cycle Jitter
Input Duty cycle over 10k cycles
Input frequency of modulation
Modulation index
Phase detector input cycle time at PDclk/M & Synclk/N
Initial phase error at phase detector inputs
Phase detector input duty cycle over 10k cycles
Input rise & fall times ( measured at 20%-80% of input voltage) for
PDCLK/M & SYNCLK/N,&REfCLK
Input capacitance at PDCLK/M,Synclk/N,&REFCLK
Input Capacitance matching at PCLK/M & SYNCLK/N
Input capacitance at CMOS pins
Input (CMOS) signal low voltage
Input (CMOS) signal high voltage
REFCLK input low voltage
REFCLK input high voltage
Input signal low voltage for PD inputs and STOP
Input signal high voltage for PD inputs and STOP
Input supply referance for REFCLK
Input supply referance vfor PD inputs
Phase detector phase error for distributed loop measured at
PDCLK/M & SYNCLK/N(rising
Cycle cycle time
Cycle-to-cycle jitter at Busclk/BUSCLKB (533 MHz)
Total jitter over 1 - 6 cycles (533MHz)
Phase aligner, phase step size (BSCLK/BUSCLKB)
PLL out put phase error when tracking SSC
Out put crossing-point voltage
Output voltage swing
Output high voltage
Out put duty cycle over 10k cycle
Output cycle -to-cycle duty cycle error
Output rise & fall times ( measured at 20%-80% of output voltage)
Difference between rise and fall times on a single device(20%-80%)
Opearting Supply Current
0272F—08/08/07
Symbol
VDD
t
CYCLE,IN
t
J,IN
DC
IN
F
m,in
P
M,IN
t
CYCLE,PD
T
err,init
D
CIN,PD
T
IR
,T
IF
C
IN,PD
DC
IN,PD
C
IN,CMOS
V
IL
V
IH
V
IL,R
V
IH,R
V
IL,PD
V
IH,PD
V
DD,IR
V
DDI,PD
t
ERR,PD
t
CYCLE
t
J
t
J
t
STEP
t
ERR,SSC
V
X
V
COS
V
H
DC
t
DC,ERR
t
CR
,t
CF
t
CR,CF
I
DD
Min
3.135
10
-
40%
30
0.25
30
-0.5
25%
-
-
-
-
-
0.7
-
0.7
-
0.7
1.3
1.3
-100
2.5
-
-
1
-100
1.3
0.4
-
40%
-
300
-
Max
3.465
40
250
60%
33
0.5
100
0.5
75%
1
7
0.5
10
0.3
-
0.3
-
0.3
-
3.465
3.465
100
3.75
40
30
-
100
1.8
0.6
2
60%
50
500
100
150
Unit
V
ns
ps
t
CYCLE
kHz
%
ns
t
CYCLE,PD
t
CYCLE,PD
ns
pF
pF
pF
Vdd
Vdd
Vddi,R
Vddi,R
Vddi,PD
Vddi,PD
V
V
ps
ns
ps
ps
ps
ps
V
V
V
t
CYCLE
ps
ps
ps
mA
4
ICS9212-13
Recommended Layout
General Layout Precautions:
1) Use a ground plane on the top layer of
the PCB in all areas not used by traces.
2) Make all power traces and vias as wide
as possible to lower inductance.
Capacitor Values:
C3 : 100pF ceramic
All unmarked capacitors are 0.01µF ceramic
Connections to VDD:
0272F—08/08/07
5
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