VIPer100/SP
VIPer100A/ASP
SMPS PRIMARY I.C.
Table 1.
Type
VIPer100/SP
VIPer100A/ASP
■
General Features
V
DSS
620V
700V
I
n
3A
3A
R
DS(on)
2.5
Ω
2.8
Ω
Figure 2.
Package
ADJUSTABLE SWITCHING FREQUENCY UP
TO 200 kHz
CURRENT MODE CONTROL
SOFT START AND SHUTDOWN CONTROL
AUTOMATIC BURST MODE OPERATION IN
STAND-BY CONDITION ABLE TO MEET
“BLUE ANGEL” NORM (<1w TOTAL POWER
CONSUMPTION)
INTERNALLY TRIMMED ZENER
REFERENCE
UNDERVOLTAGE LOCK-OUT WITH
HYSTERESIS
INTEGRATED START-UP SUPPLY
OVER-TEMPERATURE PROTECTION
LOW STAND-BY CURRENT
ADJUSTABLE CURRENT LIMITATION
PENTAWATT HV
PENTAWATT HV (022Y)
■
■
■
DESCRIPTION
■
VIPer100™/100A, made using VIPower M0
Technology, combines on the same silicon chip a
state-of-the-art PWM circuit together with an
optimized, high voltage, Vertical Power MOSFET
(620V or 700V / 3A).
Typical applications cover offline power supplies
with a secondary power capability of 50 W in wide
range condition and 100W in single range or with
doubler configuration. It is compatible from both
primary or secondary regulation loop despite
using around 50% less components when
compared with a discrete solution. Burst mode
operation is an additional feature of this device,
offering the ability to operate in stand-by mode
without extra components.
DRAIN
■
■
■
■
■
Figure 1.
Block Diagram
O
bs
l
o
te
e
ro
P
uc
d
UVLO
LOGIC
s)
t(
SECURITY
LATCH
so
b
-O
OSC
P
te
le
od
r
s)
t(
uc
ON/OFF
OSCILLATOR
PWM
LATCH
S
R1 FF Q
R2 R3
V
DD
R/S
FF
S
Q
OVERTEMP.
DETECTOR
0.5V
_
+ +
_
0.5 V
ERROR
_ AMPLIFIER
13 V
+
+
_
1.7
μ
s
DELAY
250 ns
BLANKING
1 V/A
CURRENT
AMPLIFIER
COMP
SOURCE
FC00231
4.5 V
June 2005
Rev 2
1/24
www.st.com
24
VIPer100/SP - VIPer100A/ASP
Table 2.
Symbol
Absolute Maximum Rating
Parameter
Continuous Drain-Source Voltage (TJ = 25 to 125°C)
for
VIPer100/SP
for
VIPer100A/ASP
Maximum Current
Supply Voltage
Voltage Range Input
Voltage Range Inpu
Maximum Continuous Current
Electrostatic Discharge (R =1.5kΩ; C=100pF)
Avalanche Drain-Source Current, Repetitive or Not Repetitive
(Tc=100°C; Pulse width limited by TJ max;
δ
< 1%)
for
VIPer100/SP
for
VIPer100A/ASP
Power Dissipation at T
c
=25ºC
Junction Operating Temperature
Storage Temperature
Value
Unit
V
V
A
V
V
V
mA
V
V
DS
I
D
V
DD
V
OSC
V
COMP
I
COMP
V
ESD
–0.3 to 620
–0.3 to 700
Internally limited
0 to 15
0 to V
DD
0 to 5
±2
4000
I
D(AR)
2
1.4
82
P
tot
T
j
T
stg
Table 3.
Symbol
R
thj-case
R
thj-amb
Thermal data
Parameter
Thermal Resistance Junction-case
Thermal Resistance Ambient-case
Figure 3.
Connection Diagrams (Top View)
b
O
Table 4.
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te
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P
uc
d
I
DD
s)
t(
so
b
-O
te
le
r
P
Internally limited
-65 to 150
od
1.4
60
ct
u
s)
(
A
A
W
°C
°C
PENTAWATT HV
Unit
°C/W
°C/W
Max
Max
PENTAWATT HV
PENTAWATT HV (022Y)
Current and Voltage Convention
I
D
VDD
DRAIN
I
OSC
OSC
-
13V
+
COMP SOURCE
V
DD
V
DS
I
COMP
V
OSC
V
COMP
FC00020
2/24
VIPer100/SP - VIPer100A/ASP
Table 5.
Ordering Numbers
PENTAWATT HV
VIPer100
VIPer100A
PENTAWATT HV (022Y)
VIPer100 (022Y)
VIPer100A (022Y)
Pins Functional Description
Drain Pin (Integrated Power MOSFET Drain):
Integrated Power MOSFET drain pin. It provides internal bias current during start-up via an integrated
high voltage current source which is switched off during normal operation. The device is able to handle
an unclamped current during its normal operation, assuring self protection against voltage surges, PCB
stray inductance, and allowing a snubberless operation for low output power.
Suorce Pin:
Power MOSFET source pin. Primary side circuit common ground connection.
V
DD
Pin (Power Supply):
This pin provides two functions :
■
It corresponds to the low voltage supply of the control part of the circuit. If V
DD
goes below 8V, the start-
up current source is activated and the output power MOSFET is switched off until the V
DD
voltage
reaches 11V. During this phase, the internal current consumption is reduced, the V
DD
pin is sourcing
a current of about 2mA and the COMP pin is shorted to ground. After that, the current source is shut
down, and the device tries to start up by switching again.
This pin is also connected to the error amplifier, in order to allow primary as well as secondary
regulation configurations. In case of primary regulation, an internal 13V trimmed reference voltage is
used to maintain V
DD
at 13V. For secondary regulation, a voltage between 8.5V and 12.5V will be put
on V
DD
pin by transformer design, in order to stuck the output of the transconductance amplifier to the
high state. The COMP pin behaves as a constant current source, and can easily be connected to the
output of an optocoupler. Note that any overvoltage due to regulation loop failure is still detected by the
error amplifier through the V
DD
voltage, which cannot overpass 13V. The output voltage will be
somewhat higher than the nominal one, but still under control.
■
Compensation Pin
■
This pin provides two functions :
It is the output of the error transconductance amplifier, and allows for the connection of a compensation
network to provide the desired transfer function of the regulation loop. Its bandwidth can be easily
adjusted to the needed value with usual components value. As stated above, secondary regulation
configurations are also implemented through the COMP pin.
When the COMP voltage is going below 0.5V, the shut-down of the circuit occurs, with a zero duty cycle
for the power MOSFET. This feature can be used to switch off the converter, and is automatically
activated by the regulation loop (no matter what the configuration is) to provide a burst mode operation
in case of negligible output power or open load condition.
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■
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so
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t(
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OSC Pin (Oscillator Frequency):
An R
t
-C
t
network must be connected on that to define the switching frequency. Note that despite the
connection of R
t
to V
DD
, no significant frequency change occurs for V
DD
varying from 8V to 15V. It
provides also a synchronisation capability, when connected to an external frequency source.
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