DATASHEET
PECL/CMOS TO CMOS CLOCK DRIVER
Description
The ICS558-01 accepts a high speed input of either PECL
or CMOS, integrates a divider of 1, 2, 3, or 4, and provides
four CMOS low skew outputs. The chip also has output
enables so that one, three, or all four outputs can be
tri-stated.
The ICS558-01 is a member of the IDT Clock Blocks™
family
of clock generation, synchronization, and distribution
devices.
ICS558-01
Features
•
•
•
•
•
•
•
•
•
•
16-pin TSSOP package
Pb (lead) free package
Selectable PECL or CMOS inputs
Operates up to 250 MHz
Works as a voltage translator
Four low skew (<250 ps) outputs
Selectable internal divider
Operating input voltages of 3.3 V or 5.0 V
Operating output voltages of 2.5 V, 3.3 V or 5.0 V
Ideal for IA64 designs
Block Diagram
VDDP
VDDC
OE0
PECLIN
PECLIN
CLK1
CLK2
Output Divide
CLK3
CLK4
1
CMOSIN
SELPECL
S0, S1
2
0
GND
GND
OE1
IDT™ / ICS™
PECL/CMOS TO CMOS CLOCK DRIVER
1
ICS558-01
REV F 051310
ICS558-01
PECL/CMOS TO CMOS CLOCK DRIVER
PECL CLOCK DRIVER
Pin Assignment
S0
S1
VDDP
PECLIN
PECLIN
GND
CMOSIN
OE0
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
SELPECL
VDDC
CLK1
CLK2
CLK3
CLK4
GND
OE1
Input Clock Selection
SELPECL
0
1
Input
CMOSIN
PECLIN
Tri-State Table
OE1 OE0
0
0
1
1
0
1
0
1
CLK 1
Tri-state
Clock ON
Tri-state
Clock ON
CLK 2, 3, 4
Tri-state
Tri-state
Clock ON
Clock ON
16-pin 173 Mil (0.65mm) TSSOP
Output Divide Selection
S1
0
0
1
1
S0
0
1
0
1
Output Divide
/1
/2
/3
/4
Pin Descriptions
Pin
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Pin
Name
S0
S1
VDDP
PECLIN
PECLIN
GND
CMOSIN
OE0
OE1
GND
CLK4
CLK3
CLK2
CLK1
VDDC
SELPECL
Pin Type
Input
Input
Power
Clock Input
Clock Input
Power
Clock Input
Input
Input
Power
Output
Output
Output
Output
Power
Input
Pin Description
Select 0 for output divider. See table above. Internal pull-up to VDDP.
Select 1 for output divider. See table above. Internal pull-up to VDDP.
Connect to +3.3 V or +5 V. Decouple to pin 6.
PECL input. Connect to ground if not used.
Complimentary PECL input. Connect to ground if not used.
Connect to ground.
CMOS input. Connect to ground if not used.
Output Enable 0. See table above. Internal pull-up to VDDP.
Output Enable 1. See table above. Internal pull-up to VDDP.
Connect to ground.
Low skew clock output.
Low skew clock output.
Low skew clock output.
Low skew clock output.
Connect to +2.5 V, +3.3 V, or +5 V. Decouple to pin 10.
Selects PECL or CMOS input. See table above. Internal pull-up to
VDDP.
IDT™ / ICS™
PECL/CMOS TO CMOS CLOCK DRIVER
2
ICS558-01
REV F 051310
ICS558-01
PECL/CMOS TO CMOS CLOCK DRIVER
PECL CLOCK DRIVER
External Components
The ICS558-01 requires two 0.01
µ
F capacitors between VDDP and GND, and VDDC and GND—one on each side
of the chip. These must be close to the chip to minimize lead inductance. Series termination resistors of 33Ω can be
used on the outputs (these also must be close to the chip).
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS558-01. These ratings, which are
standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these
or any other conditions above those indicated in the operational sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical
parameters are guaranteed only over the recommended operating temperature range.
Item
Supply Voltage; VDDP, VDDC (referenced to ground)
Inputs and Clock Outputs (referenced to ground)
Ambient Operating Temperature
Storage Temperature
Soldering Temperature (maximum of 10 seconds)
7.0 V
Rating
-0.5 V to VDD+0.5 V
0 to +70
°
C
-65 to +150
°
C
260
°
C
DC Electrical Characteristics
VDDP = VDDC = 3.3V
(unless stated otherwise), Ambient temperature 0 to +70
°
C
Parameter
Operating Voltage, VDDP
Operating Voltage, VDDC
Input High Voltage, CMOSIN
Input Low Voltage, CMOSIN
Input High Voltage
Input Low Voltage
Common Mode Range, PECLIN
Common Mode Range, PECLIN
Peak-to-Peak Input Voltage, PECLIN
Output High Voltage
Output Low Voltage
Output High Voltage
Output Low Voltage
Symbol
Conditions
Min.
3.0
2.375
(VDDP/2)+
1
Typ.
Max.
5.5
VDDP
Units
V
V
V
≥
VDDC
VDDP
≥
VDDC
VDDP
V
IH
V
IL
V
IH
V
IL
non-clock pins
non-clock pins
VDDP=5 V
VDDP=3.3 V
V
OH
V
OL
V
OH
V
OL
VDDC = 5 V,
I
OH
= -24 mA
VDDC = 5 V,
I
OL
= 24 mA
VDDC = 3.3 V,
I
OH
= -18 mA
VDDC = 3.3 V,
I
OL
= 18 mA
(VDDP/2)-
1
VDDP-0.5
VDDP-3.7
VDDP-2.0
0.3
VDDC-0.4
0.4
VDDC-0.4
0.4
VDDP
0.5
VDDP-0.6
VDDP-0.6
1.0
V
V
V
V
V
V
V
V
V
V
IDT™ / ICS™
PECL/CMOS TO CMOS CLOCK DRIVER
3
ICS558-01
REV F 051310
ICS558-01
PECL/CMOS TO CMOS CLOCK DRIVER
PECL CLOCK DRIVER
Parameter
Output High Voltage
Output Low Voltage
Operating Supply Current
Operating Supply Current
Short Circuit Current
On-chip pull-up resistor
Input Capacitance
Symbol
V
OH
V
OL
IDDP
IDDC
Conditions
VDDC = 2.5 V,
I
OH
= -8 mA
VDDC = 2.5 V
I
OL
= 8 mA
No load, 100
MHz input
No load, 100
MHz input
Min.
VDDC-0.4
Typ.
Max.
Units
V
0.4
22
18
+70
V
mA
mA
mA
kΩ
pF
R
PU
C
IN
250
4
AC Electrical Characteristics
VDDP = VDDC = 3.3 V
(unless stated otherwise), Ambient Temperature 0 to +70
°
C
Parameter
Input Frequency
Output Rise Time
Output Fall Time
Skew, between any output clocks
Symbol
t
OR
t
OF
Conditions
Min.
0
Typ.
Max. Units
250
800
750
MHz
ps
ps
ps
(Assumes identically
loaded outputs with
identical rise times,
measured at VDDC/2)
/1
/2
/3
/4
0
250
Propagation Delay
5.0
6.0
7.0
45
45
50
50
55
55
ns
ns
ns
ns
%
%
Output Clock Duty Cycle for /2 and /4
Output Clock Duty Cycle for /1 and /3
Thermal Characteristics (16-pin TSSOP)
Parameter
Thermal Resistance Junction to
Ambient
Symbol
θ
JA
θ
JA
θ
JA
θ
JC
Conditions
Still air
1 m/s air flow
3 m/s air flow
Min.
Typ.
78
70
68
37
Max. Units
°
C/W
°
C/W
°
C/W
°
C/W
Thermal Resistance Junction to Case
IDT™ / ICS™
PECL/CMOS TO CMOS CLOCK DRIVER
4
ICS558-01
REV F 051310
ICS558-01
PECL/CMOS TO CMOS CLOCK DRIVER
PECL CLOCK DRIVER
Package Outline and Package Dimensions
(16-pin TSSOP, 4.40 mm Body, 0.65 mm Pitch)
Package dimensions are kept current with JEDEC Publication No. 95, MO-153
16
Millimeters
Symbol
E1
Inches
Min
Max
Min
Max
E
INDEX
AREA
1 2
D
A
A1
A2
b
C
D
E
E1
e
L
a
aaa
--
1.20
0.05
0.15
0.80
1.05
0.19
0.30
0.09
0.20
4.90
5.1
6.40 BASIC
4.30
4.50
0.65 Basic
0.45
0.75
0°
8°
--
0.10
--
0.047
0.002
0.006
0.032
0.041
0.007
0.012
0.0035 0.008
0.193
0.201
0.252 BASIC
0.169
0.177
0.0256 Basic
0.018
0.030
0°
8°
--
0.004
A2
A1
A
c
-C-
e
b
SEATING
PLANE
L
aaa
C
Ordering Information
Part / Order Number
558G-01LF
558G-01LFT
Marking
558G-01LF
558G-01LF
Shipping Packaging
Tubes
Tape and Reel
Package
16-pin TSSOP
16-pin TSSOP
Temperature
0 to +70° C
0 to +70° C
"LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes
no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No
other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications
such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not
recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT
does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
IDT™ / ICS™
PECL/CMOS TO CMOS CLOCK DRIVER
5
ICS558-01
REV F 051310
微控制器 MCU
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