74LVC169
Presettable synchronous 4-bit up/down binary counter
Rev. 6 — 29 November 2012
Product data sheet
1. General description
The 74LVC169 is a synchronous presettable 4-bit binary counter which features an
internal look-ahead carry circuitry for cascading in high-speed counting applications.
Synchronous operation is provided by having all flip-flops clocked simultaneously so that
the outputs (pins Q0 to Q3) change simultaneously with each other when so instructed by
the count-enable (pins CEP and CET) inputs and internal gating. This mode of operation
eliminates the output counting spikes that are normally associated with asynchronous
(ripple clock) counters. A buffered clock (pin CP) input triggers the four flip-flops on the
LOW-to-HIGH transition of the clock.
The counter is fully programmable; that is, the outputs may be preset to any number
between 0 and its maximum count. Presetting is synchronous with the clock and takes
place regardless of the levels of the count enable inputs. A LOW level on the parallel
enable (pin PE) input disables the counter and causes the data at the Dn input to be
loaded into the counter on the next LOW-to-HIGH transition of the clock. The direction of
the counting is controlled by the up/down (pin U/D) input. When pin U/D is HIGH, the
counter counts up, when LOW, it counts down.
The look-ahead carry circuitry is provided for cascading counters for n-bit synchronous
applications without additional gating. Instrumental in accomplishing this function are two
count-enable (pins CEP and CET) inputs and a terminal count (pin TC) output. Both
count-enable (pins CEP and CET) inputs must be LOW to count. Input pin CET is fed
forward to enable the terminal count (pin TC) output. Pin TC thus enabled will produce a
LOW-level output pulse with a duration approximately equal to a HIGH level portion of
pin Q0 output. The LOW level pin TC pulse is used to enable successive cascaded
stages.
The 74LVC169 uses edge triggered J-K type flip-flops and has no constraints on changing
the control of data input signals in either state of the clock. The only requirement is that
the various inputs attain the desired state at least a set-up time before the next
LOW-to-HIGH transition of the clock and remain valid for the recommended hold time
thereafter.
The parallel load operation takes precedence over the other operations, as indicated in
the mode select table. When pin PE is LOW, the data on the input pins D0 to D3 enters
the flip-flops on the next LOW-to-HIGH transition of the clock.
NXP Semiconductors
74LVC169
Presettable synchronous 4-bit up/down binary counter
In order for counting to occur, both pins CEP and CET must be LOW and pin PE must be
HIGH. The pin U/D input determines the direction of the counting. The terminal count
output pin TC output is normally HIGH and goes LOW, provided that pin CET is LOW,
when a counter reaches 15 in the count up mode. The pin TC output state is not a function
of the count-enable parallel (pin CEP) input level. Since pin TC signal is derived by
decoding the flip-flop states, there exists the possibility of decoding spikes on pin TC. For
this reason the use of pin TC as a clock signal is not recommended; see the following
logic equations:
count enable =
CEP
CET
PE
count up: TC =
Q3
Q2
Q1
Q0
CET
U
D
count down: TC =
Q3
Q2
Q1
Q0
CET
U
D
2. Features and benefits
5 V tolerant inputs for interfacing with 5 V logic
Wide supply voltage range from 1.2 V to 3.6 V
CMOS low power consumption
Direct interface with TTL levels
Up/down counting
Two count enable inputs for n-bit cascading
Built-in look-ahead carry capability
Presettable for programmable operation
Complies with JEDEC standard:
JESD8-7A (1.65 V to 1.95 V)
JESD8-5A (2.3 V to 2.7 V)
JESD8-C/JESD36 (2.7 V to 3.6 V)
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-B exceeds 200 V
CDM JESD22-C101E exceeds 1000 V
Multiple package options
Specified from
40 C
to +85
C
and from
40 C
to +125
C
74LVC169
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 6 — 29 November 2012
2 of 24
NXP Semiconductors
74LVC169
Presettable synchronous 4-bit up/down binary counter
3. Ordering information
Table 1.
Ordering information
Temperature range
40 C
to +125
C
40 C
to +125
C
Package
Name
74LVC169D
74LVC169DB
SO16
SSOP16
TSSOP16
Description
plastic small outline package; 16 leads;
body width 3.9 mm
plastic shrink small outline package; 16 leads;
body width 5.3 mm
plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
Version
SOT109-1
SOT338-1
SOT403-1
Type number
74LVC169PW
40 C
to +125
C
74LVC169BQ
40 C
to +125
C
DHVQFN16 plastic dual in-line compatible thermal enhanced very thin SOT763-1
quad flat package; no leads; 16 terminals;
body 2.5
3.5
0.85 mm
4. Functional diagram
CTR4
M1 [LOAD]
M2 [COUNT]
3
D0
9
1
2
7
10
PE
U/D
CP
CEP
CET
Q0
14
Q1
13
Q2
12
Q3
11
3
4
5
6
1,7D
[1]
[2]
[4]
[8]
001aaa646
9
4
D1
5
D2
6
1
D3
10
7
2
M3 [UP]
M4 [DOWN]
G5
G6
3, 5 CT=15
4, 5 CT=0
15
2, 3, 5, 6+/C7
TC
15
2, 3, 5, 6−
14
13
12
11
001aaa645
Fig 1.
Logic symbol
Fig 2.
IEC logic symbol
74LVC169
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 6 — 29 November 2012
3 of 24
NXP Semiconductors
74LVC169
Presettable synchronous 4-bit up/down binary counter
D0
3
D
CP
Q
Q
14
Q0
D1
4
D
CP
Q
Q
13
Q1
D2
5
D
CP
Q
Q
12
Q2
D3
6
D
CP
Q
Q
11
Q3
PE
9
CEP 7
10
CET
CP
U/D
2
1
15
TC
001aaa649
Fig 3.
Logic diagram
74LVC169
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 6 — 29 November 2012
4 of 24
NXP Semiconductors
74LVC169
Presettable synchronous 4-bit up/down binary counter
5. Pinning information
5.1 Pinning
74LVC169
terminal 1
index area
16 V
CC
15 TC
14 Q0
13 Q1
12 Q2
GND
(1)
8
9
PE
11 Q3
10 CET
GND
U/D
2
3
4
5
6
7
1
CP
16 V
CC
15 TC
14 Q0
13 Q1
12 Q2
11 Q3
10 CET
9
001aaa644
74LVC169
U/D
CP
D0
D1
D2
D3
CEP
GND
1
2
3
4
5
6
7
8
D0
D1
D2
D3
CEP
PE
001aaa682
Transparent top view
(1) This is not a supply pin. The substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to GND.
Fig 4.
Pin configuration for SO16 and (T)SSOP16
Fig 5.
Pin configuration for DHVQFN16
5.2 Pin description
Table 2.
Symbol
U/D
CP
D0 to D3
CEP
GND
PE
CET
Q0 to Q3
TC
V
CC
Pin description
Pin
1
2
3, 4, 5, 6
7
8
9
10
14, 13, 12, 11
15
16
Description
up/down control input
clock input (LOW-to-HIGH, edge-triggered)
data input
count enable input (active LOW)
ground (0 V)
parallel enable input (active LOW)
count enable carry input (active LOW)
flip-flop output
terminal count output (active LOW)
supply voltage
74LVC169
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 6 — 29 November 2012
5 of 24
嵌入式系统
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
