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74VHCT573A Octal D-Type Latch with 3-STATE Outputs
May 2007
74VHCT573A
Octal D-Type Latch with 3-STATE Outputs
Features
■
High speed: t
PD
=
7.7ns (Typ.) at T
A
=
25°C
■
High Noise Immunity: V
IH
=
2.0V, V
IL
=
0.8V
■
Power Down Protection is provided on all inputs and
tm
General Description
The VHCT573A is an advanced high speed CMOS octal
latch with 3-STATE output fabricated with silicon gate
CMOS technology. It achieves the high speed operation
similar to equivalent Bipolar Schottky TTL while main-
taining the CMOS low power dissipation. This 8-bit
D-type latch is controlled by a Latch Enable input (LE)
and an Output Enable input (OE). When the OE input is
HIGH, the eight outputs are in a high impedance state.
Protection circuits ensure that 0V to 7V can be applied to
the input and output
(1)
pins without regard to the supply
voltage. This device can be used to interface 3V to 5V
systems and two supply systems such as battery back
up. This circuit prevents device destruction due to mis-
matched supply and input voltages.
Note:
1. Outputs in OFF-State
outputs
■
Low Noise: V
OLP
=
1.6V (Max.)
■
Low Power Dissipation: I
CC
=
4µA (Max.) @ T
A
=
25°C
■
Pin and function compatible with 74HCT573
Ordering Information
Order Number
74VHCT573AM
74VHCT573ASJ
74VHCT573AMTC
Package
Number
M20B
M20D
MTC20
Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153,
4.4mm Wide
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the
ordering number. Pb-Free package per JEDEC J-STD-020B.
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