Low Skew, 1-to16, Differential-to-2.5V
LVPECL Fanout Buffer
8530
DATA SHEET
General Description
The 8530 is a low skew, 1-to-16 Differential-to- 2.5V LVPECL Fanout
Buffer. The CLK, nCLK pair can accept most standard differential
input levels. The high gain differential amplifier accepts peak-to-peak
input voltages as small as 150mV, as long as the common mode
voltage is within the specified minimum and maximum range.
Guaranteed output and part-to-part skew characteristics make the
8530 ideal for those clock distribution applications demanding well
defined performance and repeatability.
Features
•
•
•
•
•
•
•
•
•
•
•
Sixteen differential LVPECL output pairs
CLK, nCLK input pair
CLK, nCLK pair can accept the following differential input
levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
Maximum output frequency: 500MHz
Translates any single-ended input signal to 2.5V LVPECL levels
with a resistor bias on nCLK input
Output skew: 50ps (maximum)
Part-to-part skew: 250ps (maximum)
Propagation delay: 2ns (maximum)
3.3V core, 2.5V output operating supply
0°C to 70°C ambient operating temperature
Available in lead-free (RoHS 6) package
Block Diagram
CLK
Pulldown
nCLK
Pullup
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
nQ4
Q5
nQ5
Q6
nQ6
Q7
nQ7
Q15
nQ15
Q14
nQ14
Q13
nQ13
Q12
nQ12
Q11
nQ11
Q10
nQ10
Q9
nQ9
Q8
nQ8
Pin Assignment
Q12
nQ13
Q13
V
EE
nQ14
Q14
V
CCO
nQ12
nCLK
nQ15
Q15
V
CCO
V
CCO
Q11
nQ11
Q10
nQ10
V
EE
Q9
nQ9
Q8
nQ8
V
CCO
V
CC
48 47 46 45 44 43 42 41 40 39 38 37
36
35
34
33
32
5
6
31
7
30
8
29
9
28
10
27
11
26
12
25
13 14 15 16 17 18 19 20 21 22 23 24
1
2
3
4
V
CC
V
CCO
Q7
nQ7
Q6
nQ6
V
EE
Q5
nQ5
Q4
nQ4
V
CCO
CLK
V
CCO
nQ0
Q0
nQ1
Q1
V
EE
nQ2
Q2
nQ3
Q3
V
CCO
8530
48-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
8530 REVISION G 06/26/15
1
©2015 Integrated Device Technology, Inc.
8530 DATA SHEET
Table 1. Pin Descriptions
Number
1, 11, 14, 24, 25, 35, 38, 48
2, 3
4, 5
6, 19, 30, 43
7, 8
9, 10
12, 13
15, 16
17, 18
20, 21
22, 23
26, 27
28, 29
31, 32
33, 34
36
37
39, 40
41. 42
44, 45
46, 47
Name
V
CCO
Q11, nQ11
Q10, nQ10
V
EE
Q9, nQ9
Q8, nQ8
V
CC
Q7, nQ7
Q6, nQ6
Q5, nQ5
Q4, nQ4
Q3, nQ3
Q2, nQ2
Q1, nQ1
Q0, nQ0
CLK
nCLK
Q15, nQ15
Q14, nQ14
Q13, nQ13
Q12, nQ12
Power
Output
Output
Power
Output
Output
Power
Output
Output
Output
Output
Output
Output
Output
Output
Input
Input
Output
Output
Output
Output
Pulldown
Pullup
Type
Description
Output power supply pins.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Negative power supply pins.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Positive power supply pins.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Non-inverting differential clock input.
Inverting differential clock input.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
NOTE:
Pullup and Pulldown
refer to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
k
k
LOW SKEW, 1-TO16, DIFFERENTIAL-TO-2.5V LVPECL FANOUT
BUFFER
2
REVISION G 06/26/15
8530 DATA SHEET
Function Table
Table 3. Clock Input Function Table
Inputs
CLK
0
1
0
1
Biased; NOTE 1
Biased; NOTE 1
nCLK
1
0
Biased; NOTE 1
Biased; NOTE 1
0
1
Outputs
Q[0:15]
LOW
HIGH
LOW
HIGH
HIGH
LOW
nQ[0:15]
HIGH
LOW
HIGH
LOW
LOW
HIGH
Input to Output Mode
Differential to Differential
Differential to Differential
Single-Ended to Differential
Single-Ended to Differential
Single-Ended to Differential
Single-Ended to Differential
Polarity
Non-Inverting
Non-Inverting
Non-Inverting
Non-Inverting
Inverting
Inverting
NOTE 1: Refer to the Application Information section,
Wiring the Differential Input to Accept single-ended Levels.
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics or AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Supply Voltage, V
CC
Inputs, V
I
Outputs, I
O
Continuous Current
Surge Current
Package Thermal Impedance,
JA
Storage Temperature, T
STG
Rating
4.6V
-0.5V to V
CC
+ 0.5V
50mA
100mA
47.9°C/W (0 lfpm)
-65C to 150C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, V
CC
= 3.3V ± 5%, V
CCO
= 2.5V ± 5%, V
EE
= 0V, T
A
= 0°C to 70°C
Symbol
V
CC
V
CCO
I
EE
Parameter
Positive Supply Voltage
Output Supply Voltage
Power Supply Current
Test Conditions
Minimum
3.135
2.375
Typical
3.3
25
Maximum
3.465
2.625
150
Units
V
V
mA
LOW SKEW, 1-TO16, DIFFERENTIAL-TO-2.5V LVPECL FANOUT
BUFFER
3
REVISION G 06/26/15
8530 DATA SHEET
Table 4B. Differential Input DC Characteristics, V
CC
= 3.3V ± 5%, V
CCO
= 2.5V ± 5%, V
EE
= 0V, T
A
= 0°C to 70°C
Symbol
I
IH
Parameter
CLK
Input High Current
nCLK
CLK
I
IL
V
PP
V
CMR
Input Low Current
nCLK
Peak-to-Peak Input Voltage
Common Mode Input Voltage; NOTE 1
-150
0.15
0.05
1.3
V
CC
– 0.85
µA
V
V
-5
5
µA
µA
Test Conditions
Minimum
Typical
Maximum
150
Units
µA
NOTE 1: Common mode input voltage is defined as V
IH
.
Table 4C. LVPECL DC Characteristics, V
CC
= 3.3V ± 5%, V
CCO
= 2.5V ± 5%, V
EE
= 0V, T
A
= 0°C to 70°C
Symbol
V
OH
V
OL
V
SWING
Parameter
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Peak-to-Peak Output Voltage Swing
Test Conditions
Minimum
V
CCO
– 1.1
V
CCO
– 2.0
0.55
Typical
Maximum
V
CCO
– 0.7
V
CCO
– 1.4
0.93
Units
V
V
V
NOTE 1: Outputs terminated with 50 to V
CCO
– 2V.
AC Electrical Characteristics
Table 5. AC Electrical Characteristics, V
CC
= 3.3V ± 5%, V
CCO
= 2.5V ± 5%, V
EE
= 0V, T
A
= 0°C to 70°C
Symbol
f
MAX
Parameter
Output Frequency
Test Conditions
ƒ
500MHz
Minimum
1
Typical
Maximum
500
2
Units
MHz
ns
ps
ps
ps
%
t
PD
tsk(o)
tsk(pp)
t
R
/ t
F
odc
Propagation Delay; NOTE 1
Output Skew; NOTE 2, 3
Part-to-Part Skew; NOTE 2, 4
Output Rise/ Fall Time
Output Duty Cycle
26
20% to 80% @ 50MHz
300
47
50
50
250
700
53
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. Device will meet specifications after thermal equilibrium has
been reached under these conditions.
NOTE All parameters measured at 250MHz unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential cross
points.
NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltage, same temperature and with equal load
conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points.
LOW SKEW, 1-TO16, DIFFERENTIAL-TO-2.5V LVPECL FANOUT
BUFFER
4
REVISION G 06/26/15
8530 DATA SHEET
Parameter Measurement Information
2.8V±0.04V
2V
V
CC
V
CCO
V
CC
Qx
SCOPE
nCLK
V
PP
Cross Points
V
LVPECL
V
EE
nQx
CMR
CLK
V
EE
-0.5V±0.125V
3.3V Core/ 2.5V LVPECL Output Load AC Test Circuit
Differential Input Level
nQx
nQx
Qx
Qx
nQy
nQy
Qy
Qy
Par t 1
Par t 2
tsk(pp)
Output Skew
Part-to-Part Skew
nQ[0:15]
Q[0:15]
nCLK
CLK
nQ[0:15]
Q[0:15]
t
PD
Output Duty Cycle/Pulse Width/Period
Propagation Delay
LOW SKEW, 1-TO16, DIFFERENTIAL-TO-2.5V LVPECL FANOUT
BUFFER
5
REVISION G 06/26/15
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