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74HCT112N652

产品描述Flip Flops DUAL J-K NEG EDGE
产品类别半导体    逻辑   
文件大小774KB,共20页
制造商NXP(恩智浦)
官网地址https://www.nxp.com
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74HCT112N652概述

Flip Flops DUAL J-K NEG EDGE

74HCT112N652规格参数

参数名称属性值
产品种类
Product Category
Flip Flops
制造商
Manufacturer
NXP(恩智浦)
RoHSDetailscfvctebeaxasvaddfvrwscbs
Number of Circuits2
Logic FamilyHCT
Logic TypeJ-K Negative Edge Triggered Flip-Flop
PolarityInverting/Non-Inverting
Input TypeSingle-Ended
输出类型
Output Type
Differential
传播延迟时间
Propagation Delay Time
19 ns
High Level Output Current- 6 mA
Low Level Output Current6 mA
电源电压-最大
Supply Voltage - Max
5.5 V
最小工作温度
Minimum Operating Temperature
- 40 C
最大工作温度
Maximum Operating Temperature
+ 125 C
安装风格
Mounting Style
Through Hole
封装 / 箱体
Package / Case
PDIP-16
系列
Packaging
Tube
FunctionJK Type
高度
Height
3.2 mm
长度
Length
19.5 mm
Number of Channels2
Number of Input Lines2
Number of Output Lines1
工作电源电压
Operating Supply Voltage
5 V
Quiescent Current4 uA
Reset TypeSet, Reset
工厂包装数量
Factory Pack Quantity
1000
电源电压-最小
Supply Voltage - Min
4.5 V
宽度
Width
6.48 mm
单位重量
Unit Weight
0.057419 oz

文档预览

下载PDF文档
74HC112; 74HCT112
Dual JK flip-flop with set and reset; negative-edge trigger
Rev. 3 — 9 August 2016
Product data sheet
1. General description
The 74HC112; 74HCT112 is a dual negative-edge triggered JK flip-flop. It features
individual J and K inputs, clock (nCP) set (nSD) and reset (nRD) inputs. It also has
complementary nQ and nQ outputs. The set and reset are asynchronous active LOW
inputs and operate independently of the clock input. The J and K inputs control the state
changes of the flip-flops as described in the mode select function table. The J and K
inputs must be stable one set-up time prior to the HIGH-to-LOW clock transition for
predictable operation. Inputs include clamp diodes that enable the use of current limiting
resistors to interface inputs to voltages in excess of V
CC
.
Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock
rise and fall times.
2. Features and benefits
Input levels:
For 74HC112: CMOS level
For 74HCT112: TTL level
Asynchronous set and reset
Specified in compliance with JEDEC standard no. 7A
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
Multiple package options
Specified from
40 C
to +85
C
and from
40 C
to +125
C
3. Ordering information
Table 1.
Ordering information
Package
Temperature range
74HC112D
74HCT112D
74HC112DB
74HCT112DB
74HC112PW
74HCT112PW
40 C
to +125
C
40 C
to +125
C
SSOP16
plastic shrink small outline package; 16 leads; body width
5.3 mm
SOT338-1
SOT403-1
40 C
to +125
C
Name
SO16
Description
Version
plastic small outline package; 16 leads; body width 3.9 mm SOT109-1
Type number
TSSOP16 plastic thin shrink small outline package; 16 leads;
body width 4.4 mm

74HCT112N652相似产品对比

74HCT112N652 74HC112PW118 74HC112N652 74HC112DB112 74HCT112DB118
描述 Flip Flops DUAL J-K NEG EDGE Multilayer Ceramic Capacitors MLCC - SMD/SMT 50volts 1500pF 10% X7R AUTO Flip Flops DUAL J-K NEG EDGE Flip Flops DUAL J-K NEG EDGE Flip Flops DUAL J-K NEG EDGE
产品种类
Product Category
Flip Flops Flip Flops Flip Flops Flip Flops Flip Flops
制造商
Manufacturer
NXP(恩智浦) NXP(恩智浦) NXP(恩智浦) NXP(恩智浦) NXP(恩智浦)
RoHS Detailscfvctebeaxasvaddfvrwscbs Details Details Details Details
Number of Circuits 2 2 2 2 2
Logic Family HCT HC HC HC HCT
Logic Type J-K Negative Edge Triggered Flip-Flop J-K Negative Edge Triggered Flip-Flop J-K Negative Edge Triggered Flip-Flop J-K Negative Edge Triggered Flip-Flop J-K Negative Edge Triggered Flip-Flop
Polarity Inverting/Non-Inverting Inverting/Non-Inverting Inverting/Non-Inverting Inverting/Non-Inverting Inverting/Non-Inverting
Input Type Single-Ended Single-Ended Single-Ended Single-Ended Single-Ended
输出类型
Output Type
Differential Differential Differential Differential Differential
传播延迟时间
Propagation Delay Time
19 ns 17 ns at 5 V 17 ns at 5 V 17 ns at 5 V 19 ns
High Level Output Current - 6 mA - 7.8 mA - 7.8 mA - 7.8 mA - 6 mA
Low Level Output Current 6 mA 7.8 mA 7.8 mA 7.8 mA 6 mA
电源电压-最大
Supply Voltage - Max
5.5 V 6 V 6 V 6 V 5.5 V
最小工作温度
Minimum Operating Temperature
- 40 C - 40 C - 40 C - 40 C - 40 C
最大工作温度
Maximum Operating Temperature
+ 125 C + 125 C + 125 C + 125 C + 125 C
安装风格
Mounting Style
Through Hole SMD/SMT SMD/SMT SMD/SMT SMD/SMT
封装 / 箱体
Package / Case
PDIP-16 SOT-403 SOT-38 SOT-338 SOT-338
Function JK Type JK Type JK Type JK Type JK Type
高度
Height
3.2 mm 0.95 mm 3.2 mm 1.8 mm 1.8 mm
长度
Length
19.5 mm 5.1 mm 19.5 mm 6.4 mm 6.4 mm
Number of Channels 2 2 2 2 2
Number of Input Lines 2 2 2 2 2
Number of Output Lines 1 1 1 1 1
工作电源电压
Operating Supply Voltage
5 V 5 V 5 V 5 V 5 V
Quiescent Current 4 uA 4 uA 4 uA 4 uA 4 uA
Reset Type Set, Reset Set, Reset Set, Reset Set, Reset Set, Reset
工厂包装数量
Factory Pack Quantity
1000 2500 1000 1092 2000
电源电压-最小
Supply Voltage - Min
4.5 V 2 V 2 V 2 V 4.5 V
宽度
Width
6.48 mm 4.5 mm 6.48 mm 5.4 mm 5.4 mm
系列
Packaging
Tube Cut Tape Tube Tube Cut Tape

 
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